software/arm-trusted-firmware.git/drivers/cadence/emmc/cdns_sdmmc.c, branch masterTrusted Firmware-Ahttps://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/atom?h=master2026-09-02T11:36:44+00:00fix(cadence): use device-specific SDMMC default clocks2026-09-02T11:36:44+00:00Bryan Chan Jia Chingbryan.chan@altera.com2026-04-22T16:00:00+00:00urn:sha1:8ebc0d650c772351d936520a9bdf040935e4844b
SD cards and eMMC devices have different safe default clock rates. The
Cadence driver used the same rate for both protocols and also selected
an incorrect bus voltage during card reset.
Use 50 MHz for high-speed SD cards and the 26 MHz legacy rate for eMMC.
Select the reset voltage according to the device type and consolidate
the clock setup in the SDMMC driver.
Change-Id: I6d2f5ed9d1df8661cd39076f77bca8d01387df5f
Signed-off-by: Bryan Chan Jia Ching <bryan.chan@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
fix(intel): fix eMMC driver issues in boot flow on agilex52025-08-08T12:17:47+00:00Boon Khai Ngboon.khai.ng@altera.com2025-07-01T11:16:46+00:00urn:sha1:38636fea416bf90b651a6623f94d2637282f9444
Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.
Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.
Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.
eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.
Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor2025-08-07T02:31:52+00:00Boon Khai Ngboon.khai.ng@altera.com2025-07-29T09:29:43+00:00urn:sha1:2fcb37db8384bfb7a08edcd024f5ca4e245dc2df
When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sending MMC command. The memory is not aligned correctly
when using different version of gcc.
The descriptor memory must be aligned to 4 byte boundary
with 2 least significant bits set to 0 in 32-bit ADMA
addressing mode and aligned to 8 byte boundary with
3 least significant bits set to 0 in 64-bit ADMA
addresing mode.
Since 8 byte boundary is common to both 4 byte and
8 byte boundary hence aligning the descriptor
memory with 8 byte boundary.
Change-Id: Ie56d2aef22b4e4ef0fa516b9cda53b33d6316cb7
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
fix(intel): refactor SDMMC driver for Altera products2024-10-25T01:38:51+00:00Sieu Mun Tangsieu.mun.tang@intel.com2024-10-25T01:37:42+00:00urn:sha1:beba20403e23ab128711c2c8c9d480a3a40b804c
Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.
Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA2023-07-05T02:11:11+00:00Jit Loon Limjit.loon.lim@intel.com2023-05-17T04:26:11+00:00urn:sha1:ddaf02d17142187d9f17acd4900aafa598666317
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6