software/arm-trusted-firmware.git/include/drivers/cadence/cdns_combo_phy.h, branch masterTrusted Firmware-Ahttps://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/atom?h=master2026-09-02T11:36:44+00:00fix(cadence): use device-specific SDMMC default clocks2026-09-02T11:36:44+00:00Bryan Chan Jia Chingbryan.chan@altera.com2026-04-22T16:00:00+00:00urn:sha1:8ebc0d650c772351d936520a9bdf040935e4844b
SD cards and eMMC devices have different safe default clock rates. The
Cadence driver used the same rate for both protocols and also selected
an incorrect bus voltage during card reset.
Use 50 MHz for high-speed SD cards and the 26 MHz legacy rate for eMMC.
Select the reset voltage according to the device type and consolidate
the clock setup in the SDMMC driver.
Change-Id: I6d2f5ed9d1df8661cd39076f77bca8d01387df5f
Signed-off-by: Bryan Chan Jia Ching <bryan.chan@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
fix(intel): update nand driver to enable Linux OS boot2025-10-06T06:22:06+00:00Girisha Dengigirisha.dengi@altera.com2025-06-29T18:29:43+00:00urn:sha1:6f7f8b18e9641d34c5b02b5f5e050d6e0fae12fc
Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.
Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA2023-07-05T02:11:11+00:00Jit Loon Limjit.loon.lim@intel.com2023-05-17T04:26:11+00:00urn:sha1:ddaf02d17142187d9f17acd4900aafa598666317
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6