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<title>software/arm-trusted-firmware.git/include/lib, branch master</title>
<subtitle>Trusted Firmware-A</subtitle>
<id>https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/atom?h=master</id>
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<updated>2026-09-07T11:41:30+00:00</updated>
<entry>
<title>fix(xlat): check definition of PLAT_XLAT_TABLES_DYNAMIC flag</title>
<updated>2026-09-07T11:41:30+00:00</updated>
<author>
<name>Yann Gautier</name>
<email>yann.gautier@st.com</email>
</author>
<published>2026-09-01T15:32:55+00:00</published>
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<id>urn:sha1:172467a75e8b259e8493b51291cc92fd2c93e0dc</id>
<content type='text'>
When enabling -Wundef, we can see this warning:
include/lib/xlat_tables/xlat_tables_v2_helpers.h:81:5: error:
 'PLAT_XLAT_TABLES_DYNAMIC' is not defined, evaluates to '0'
 [-Werror=undef]
   81 | #if PLAT_XLAT_TABLES_DYNAMIC
      |     ^~~~~~~~~~~~~~~~~~~~~~~~

As the flag can be defined either with `call add_defines`, or directly
added to BL*_CFLAGS, the easier way to correct those warning is to
first check the flag is defined and then that it is set, with:
`#if defined(PLAT_XLAT_TABLES_DYNAMIC) &amp;&amp; PLAT_XLAT_TABLES_DYNAMIC`

Change-Id: Ifbd20161d90e3eab46352393760fb0c01d24785c
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>fix(el3-runtime): add some missing prototypes</title>
<updated>2026-09-07T11:41:30+00:00</updated>
<author>
<name>Yann Gautier</name>
<email>yann.gautier@st.com</email>
</author>
<published>2026-09-01T14:26:05+00:00</published>
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<id>urn:sha1:04af9c91b343f0e4ff747b1aac6af1095a3c8a9c</id>
<content type='text'>
When compiling with -Werror=missing-prototypes, 2 functions are missing
their prototypes in header file: handler_interrupt_exception() and
handler_sync_exception(). Add them in runtime_svc.h.
The stdint.h include is also added to context_el1.h, or else there are
compilation errors for uint64_t being undefined.
And it is moved before ENABLE_FEAT_D128 flag in sysreg128.h, as
uint64_t is also used in the #else part.

Change-Id: I88177af229430b19715557c39da64ae0780d43d4
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>fix(libc): define __BSD_VISIBLE to 0</title>
<updated>2026-09-07T11:37:22+00:00</updated>
<author>
<name>Yann Gautier</name>
<email>yann.gautier@st.com</email>
</author>
<published>2026-08-28T16:01:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=a6d10d2c521fb0614869866f2f6782fb5c3bb5a0'/>
<id>urn:sha1:a6d10d2c521fb0614869866f2f6782fb5c3bb5a0</id>
<content type='text'>
This is defined (under conditions) in sys/cdefs.h, but the file is never
used, we have a cdefs.h in include/lib/libc instead. As the flag is not
used, and can cause compilation warning when including endian.h, define
it to 0 in the cdefs.h file we use.

Change-Id: I049f6ed9d584c33082882f5937a8a858cae93466
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>feat(cpus): add support for the Cortex-X1C CPU</title>
<updated>2026-08-20T06:56:05+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-08-05T16:35:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=33f77db3e9b279d11523e455e14880676d6e1cbf'/>
<id>urn:sha1:33f77db3e9b279d11523e455e14880676d6e1cbf</id>
<content type='text'>
This is a C variant of the Cortex-X1 core. Copy its enablement and port
any errata that also apply - most of the errata on the original are not
present on the C variant.

Change-Id: Idd8eba7e99abd0839eafde53bd69d9b20a88ed1a
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
<entry>
<title>feat(cpus): add support for the Cortex-A520AE CPU</title>
<updated>2026-08-20T06:56:05+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-08-05T15:51:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=fa97cc832301e8dad1bcce13837be519cd7f9771'/>
<id>urn:sha1:fa97cc832301e8dad1bcce13837be519cd7f9771</id>
<content type='text'>
This is an AE variant of the Cortex-A520 core. Copy its enablement and
port any errata that also apply - most of the errata on the original are
not present on the AE variant.

Change-Id: Ic34b7e3b5e4a9defe79c11be0b3251f6275b5303
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
<entry>
<title>feat(cpus): add support the Venom AE CPU</title>
<updated>2026-08-20T06:56:05+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-08-05T15:18:49+00:00</published>
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<id>urn:sha1:2723282200252c11aa81a27fbc7a5282c25ce620</id>
<content type='text'>
This is an AE variant of the Venom CPU.

Change-Id: Id50f44a42acdddb6e2b8188bab9970019b71838c
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
<entry>
<title>refactor(cpus): align AE variant core names</title>
<updated>2026-08-20T06:52:51+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-08-05T10:38:18+00:00</published>
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<id>urn:sha1:f3e4ef6b6debddf836aef0ed2a259e206096b908</id>
<content type='text'>
We've ended up with two ways of naming AE variants of cores:
&lt;cpu_name&gt;ae and &lt;cpu_name&gt;_ae. Standardise around the first one for
consistency with the C variants of cores.

Change-Id: I999ed43421d083af148c3e92cef9d8ca5c635277
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
<entry>
<title>Merge changes I6ca4b63c,I69e7ead3,I00b76de0 into integration</title>
<updated>2026-08-18T12:11:59+00:00</updated>
<author>
<name>Manish Pandey</name>
<email>manish.pandey2@arm.com</email>
</author>
<published>2026-08-18T12:11:59+00:00</published>
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<id>urn:sha1:bcfaeccf78d890b4bcc451ece96af32548c64193</id>
<content type='text'>
* changes:
  fix(cpus): add workaround for C1-Nano erratum 4497400
  fix(cpus): add workaround for Cortex-A520 erratum 4491980
  fix(cpus): add workaround for Cortex-A510 erratum 4568615
</content>
</entry>
<entry>
<title>fix(cpus): workaround for C1-Pro erratum 3773617</title>
<updated>2026-08-04T13:11:53+00:00</updated>
<author>
<name>Matthew Ellis</name>
<email>Matthew.Ellis@arm.com</email>
</author>
<published>2026-07-16T15:07:17+00:00</published>
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<id>urn:sha1:85e9f6dc95ff6fd719d9bc1c412b64404d2a8d43</id>
<content type='text'>
C1-Pro erratum 3773617 affects revision r1p1 and is fixed in
revision r1p2. It causes ICH_VMCR_EL2.VBPR1 to return incorrect data
when it is written with one SCR_EL3.NS value and subsequently read
with the other.

The required SCR_EL3.NS handling when saving and restoring ICH_VMCR_EL2
is already implemented. Register C1-Pro erratum 3773617 with the
existing common workaround so that it is applied on r1p1.

Refer https://support.arm.com/documentation/SDEN-3273080/latest

Change-Id: I9b83add5d104f4621520c8e90777f10c7a97dad5
Signed-off-by: Matthew Ellis &lt;Matthew.Ellis@arm.com&gt;
</content>
</entry>
<entry>
<title>fix(cpus): add workaround for Cortex-A510 erratum 4568615</title>
<updated>2026-08-03T14:21:55+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-08-03T13:35:51+00:00</published>
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<id>urn:sha1:1f8c2928c9a5b2323fc39b59439fce2339ff88e8</id>
<content type='text'>
The weakness is that EL3's secret data may be exposed to a lower EL via
a side channel. The workaround is to overwrite any data in this side
channel with publicly visible data using a core specific sequence.

SDEN: https://support.arm.com/documentation/SDEN-1873351

Change-Id: I00b76de0a51e60b818c271c6341bcf6682e25da6
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
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