<feed xmlns='http://www.w3.org/2005/Atom'>
<title>software/arm-trusted-firmware.git/lib/cpus/aarch64/c1_ultra.S, branch master</title>
<subtitle>Trusted Firmware-A</subtitle>
<id>https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/atom?h=master</id>
<link rel='self' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/'/>
<updated>2026-09-07T08:32:51+00:00</updated>
<entry>
<title>chore(cpus): update developer.arm.com links to support.arm.com</title>
<updated>2026-09-07T08:32:51+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-09-04T09:23:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=563bc08e9be6553b941ca9e5da94e21b95335038'/>
<id>urn:sha1:563bc08e9be6553b941ca9e5da94e21b95335038</id>
<content type='text'>
This is the new canonical place to find CPU related documentation.

Change-Id: I69d13bd8bdf99b8404b3dc78164e057d4e1f2c35
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
<entry>
<title>feat(cpus): add links to each core's TRM and SDEN</title>
<updated>2026-08-20T06:52:51+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-06-22T11:45:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=7f9703a0de085582e76dce152282be9e717b9a90'/>
<id>urn:sha1:7f9703a0de085582e76dce152282be9e717b9a90</id>
<content type='text'>
To do anything with a core you need either its TRM or SDEN (or both if
working around errata). There is no simple way to download the latest of
either of these documents in bulk so finding and downloading these
documents is a big (and somewhat annoying) part of maintaining core
drivers.

This patch tries to alleviate this problem by adding links to both of
these documents in a standard format within each CPU driver. A
convenient side effect is that this makes automation around them
possible.

Change-Id: I6fe089876aa2d764a67733041751202e2bd3c350
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
<entry>
<title>docs(cpus): add erratum 4015814 comments</title>
<updated>2026-08-17T16:31:41+00:00</updated>
<author>
<name>Matthew Ellis</name>
<email>Matthew.Ellis@arm.com</email>
</author>
<published>2026-08-11T14:09:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=88b8c9bd6dcefe8fd88de812f1e7d1b57774fed0'/>
<id>urn:sha1:88b8c9bd6dcefe8fd88de812f1e7d1b57774fed0</id>
<content type='text'>
C1-Ultra erratum 4015814 can prevent an external debugger from
accessing memory-mapped debug registers when MDCR_EL3.ETADE, EDADE,
or EPMADE are set while FEAT_RME is not implemented or enabled.

Document that the generic MDCR_EL3 initialization leaves these fields
clear, avoiding the erratum. Register the erratum as always chosen for
the affected C1-Ultra revisions.

This is documentation only; no C1-Ultra-specific workaround is
required.

SDEN documentation:
https://support.arm.com/documentation/111077/latest

Change-Id: I899d1c54cf152159e494a73f7fa962eab32d4d1d
Signed-off-by: Matthew Ellis &lt;Matthew.Ellis@arm.com&gt;
</content>
</entry>
<entry>
<title>docs(xlat): add erratum 3683289 comments</title>
<updated>2026-08-17T16:31:33+00:00</updated>
<author>
<name>Matthew Ellis</name>
<email>Matthew.Ellis@arm.com</email>
</author>
<published>2026-08-04T11:11:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=df90255531e29e9a4d0b2def77217edc4694ea2c'/>
<id>urn:sha1:df90255531e29e9a4d0b2def77217edc4694ea2c</id>
<content type='text'>
C1 Ultra erratum 3683289 can be triggered when software managing
translation tables misprograms the contiguous hint, or replaces an
existing block mapping with a different mapping without following
break-before-make and TLB invalidation requirements.

Add comments to the xlat v2 code documenting the invariants that
prevent those conditions in TF-A:
- xlat v2 does not set the contiguous hint.
- dynamic mappings only create entries where the descriptor is invalid.
- dynamic mappings do not overwrite existing block/page descriptors.
- unmap and attribute-change paths invalidate descriptors before TLB
  invalidation, with the attribute-change path using break-before-make.

This is documentation only; no C1 Ultra-specific workaround is
required.

SDEN documentation:
https://support.arm.com/documentation/111077/latest

Change-Id: Idb4a6f864967b25b5187dd882fb47abfa2bc4605
Signed-off-by: Matthew Ellis &lt;Matthew.Ellis@arm.com&gt;
LTS-candidate: yes
</content>
</entry>
<entry>
<title>fix(cpus): use #ifdef for IMAGE_BL flags</title>
<updated>2026-06-22T16:51:10+00:00</updated>
<author>
<name>Yann Gautier</name>
<email>yann.gautier@st.com</email>
</author>
<published>2026-05-28T14:01:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=76d5416966ef366b4c752886c952dbed229f2a6f'/>
<id>urn:sha1:76d5416966ef366b4c752886c952dbed229f2a6f</id>
<content type='text'>
The different flags IMAGE_BL{1,2,31,32...} are only defined and not
assigned a value. The correct way to handle it is with `#if defined`.
This corrects warnings found with -Wundef GCC flag.

Change-Id: I5a4e2acdd007ba56039b992bde77d2a9400301cd
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>fix: workaround for CVE-2025-10263</title>
<updated>2026-06-11T15:36:54+00:00</updated>
<author>
<name>John Powell</name>
<email>john.powell@arm.com</email>
</author>
<published>2025-10-15T18:21:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=08fab0f083db753682a12dae3c00eedb20f02620'/>
<id>urn:sha1:08fab0f083db753682a12dae3c00eedb20f02620</id>
<content type='text'>
This patch applies the workaround for CVE-2025-10263 to Arm
Trusted Firmware in EL3. The issue can occur when a shareable
TLBI is followed by a DSB instruction, and the workaround is
to insert an additional shareable TLBI followed by a DSB.

This issue is a little bit unique in that if even a single core
in a system is affected, then all cores must perform the
workaround. The build flag defaults to zero but must be set to 1
in the platform makefile of any affected platform.

This first iteration of the patch does not touch the GPT library
code since it is not currently used in any production hardware.

Disclosure: https://developer.arm.com/documentation/112137

Change-Id: Id4c0acee41a40a9fbf780792153e5ef328ba8807
Signed-off-by: John Powell &lt;john.powell@arm.com&gt;
</content>
</entry>
<entry>
<title>fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID</title>
<updated>2026-03-25T10:27:26+00:00</updated>
<author>
<name>Boyan Karatotev</name>
<email>boyan.karatotev@arm.com</email>
</author>
<published>2026-03-02T17:57:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=93c7e701917c2658f9063a9eaeb1336588b1e4c4'/>
<id>urn:sha1:93c7e701917c2658f9063a9eaeb1336588b1e4c4</id>
<content type='text'>
The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev &lt;boyan.karatotev@arm.com&gt;
</content>
</entry>
<entry>
<title>fix(security): avoid CVE_2025_0647 for bl2 build</title>
<updated>2026-02-19T16:49:05+00:00</updated>
<author>
<name>Yann Gautier</name>
<email>yann.gautier@st.com</email>
</author>
<published>2026-02-13T17:17:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=ec4f10c0c537a2d99818c2594c85df2e1125216d'/>
<id>urn:sha1:ec4f10c0c537a2d99818c2594c85df2e1125216d</id>
<content type='text'>
If a platform defines the flag RESET_TO_BL2, BL2 will include the CPU
library files. If the CPU is Armv8.5 or higher, the workaround flag
WORKAROUND_CVE_2025_0647 will be enable. And then there are compilation
issues, as some symbols from wa_cve_2025_0647_cpprctx.S are not found.
This has been seen on lts-v2.12 branch when preparing lts-v2.12.11 tag.
The platform RD1AE failed to compiled.

To fix this issue add the workaround only for BL31 image build, this is
similar to `override_vector_table` already done in parts of cpu lib.

Change-Id: Icdf63de6ed8413761561406eceaeddd69118b144
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
Signed-off-by: Govindraj Raja &lt;govindraj.raja@arm.com&gt;
</content>
</entry>
<entry>
<title>fix(cpus): remove C1-Ultra erratum 3651221</title>
<updated>2026-01-27T20:04:21+00:00</updated>
<author>
<name>Arvind Ram Prakash</name>
<email>arvind.ramprakash@arm.com</email>
</author>
<published>2026-01-26T17:37:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=5b7afcb3eda8bab345c7552f81c6583df0b82f60'/>
<id>urn:sha1:5b7afcb3eda8bab345c7552f81c6583df0b82f60</id>
<content type='text'>
This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Ultra erratum 3651221 [2] support.

[1] : https://developer.arm.com/documentation/110326/latest/
[2] : https://developer.arm.com/documentation/111077/latest/
Signed-off-by: Arvind Ram Prakash &lt;arvind.ramprakash@arm.com&gt;
Change-Id: If7ea433e4614f92333e788e3f6b366db22c92f0d
</content>
</entry>
<entry>
<title>fix(security): add CVE-2025-0647 for C1-Ultra</title>
<updated>2026-01-23T21:14:36+00:00</updated>
<author>
<name>Govindraj Raja</name>
<email>govindraj.raja@arm.com</email>
</author>
<published>2026-01-22T21:44:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/arm/software/arm-trusted-firmware.git/commit/?id=2bf674ef6ec6b9aa3852e4ccf7c458d6a31e385b'/>
<id>urn:sha1:2bf674ef6ec6b9aa3852e4ccf7c458d6a31e385b</id>
<content type='text'>
This patch mitigates CVE-2025-0647 for C1-Ultra CPU.

Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546

Change-Id: I506007ec8702b183e377be50eede72d6803b344b
Signed-off-by: Govindraj Raja &lt;govindraj.raja@arm.com&gt;
Signed-off-by: John Powell &lt;john.powell@arm.com&gt;
</content>
</entry>
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