diff options
59 files changed, 170 insertions, 182 deletions
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c index e4cad2f3e..940ec8834 100644 --- a/bl31/bl31_traps.c +++ b/bl31/bl31_traps.c @@ -26,7 +26,7 @@ int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx, u_register_t flags) { uint64_t opcode = EXTRACT(ESR_ISS, esr_el3) & ~(MASK(ISS_SYS64_DIR) | MASK(ISS_SYS64_RT)); uint8_t rt = EXTRACT(ISS_SYS64_RT, esr_el3); - bool is_read = EXTRACT(ISS_SYS64_DIR, opcode); + bool is_read = EXTRACT(ISS_SYS64_DIR, esr_el3); if (is_feat_idte3_supported() && ((opcode >= ISS_SYSREG_OPCODE_IDREG_MIN && @@ -113,7 +113,7 @@ int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx, u_register_t flags) * The code here is based on pseudocode described in the Arm ARM (DDI0487). They * can also be found in the Arm A-profile A64 Instruction Set Architecture * document (DDI0602) available at - * https://developer.arm.com/documentation/ddi0602/latest/. + * https://support.arm.com/documentation/ddi0602/latest/Shared-Pseudocode. * * NOTE: This piece of code must be reviewed every release against the latest * sequence to ensure that we keep up with new arch features. diff --git a/drivers/cadence/combo_phy/cdns_combo_phy.c b/drivers/cadence/combo_phy/cdns_combo_phy.c index f00d0c100..87f176f9c 100644 --- a/drivers/cadence/combo_phy/cdns_combo_phy.c +++ b/drivers/cadence/combo_phy/cdns_combo_phy.c @@ -64,20 +64,3 @@ int cdns_sd_card_detect(void) return 0; } - -int cdns_emmc_card_reset(void) -{ - uint32_t _status = 0; - - /* Reset embedded card */ - mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); - mdelay(68680); /* ~68680us */ - mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP)); - udelay(340); /* ~340us */ - - /* Turn on supply voltage */ - /* BVS = 7, BP = 1, BP2 only in UHS2 mode */ - mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); - - return 0; -} diff --git a/drivers/cadence/emmc/cdns_sdmmc.c b/drivers/cadence/emmc/cdns_sdmmc.c index 1dd81f8ed..b984cf5d4 100644 --- a/drivers/cadence/emmc/cdns_sdmmc.c +++ b/drivers/cadence/emmc/cdns_sdmmc.c @@ -427,20 +427,23 @@ void sd_host_oper_mode(enum sd_opr_modes opr_mode) } } -void card_reset(bool power_enable) +void cdns_sdmmc_card_reset(void) { uint32_t reg_value = 0; - /* Reading SRS10 value before writing */ + /* Power off: per SDHCI/JEDEC spec, BVS must be cleared when BP=0 */ reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10); + reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); + mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value); + mdelay(20); - if (power_enable == true) { - reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); - reg_value = ((1 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); - } else { - reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); - } + /* + * BVS=0b111 = 3.3V ; BVS=0b101 = 1.8V + * Using 3.3V for High Speed(SD)/legacy(eMMC) protocol. + */ + reg_value |= ((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value); + mdelay(50); } void high_speed_enable(bool mode) @@ -501,14 +504,8 @@ void sdmmc_host_init(bool uhs2_enable) /** need to implement*/ } - /* Card reset */ - - card_reset(1); - udelay(2500); - card_reset(0); - udelay(2500); - card_reset(1); - udelay(2500); + /* Card reset - for both eMMC and SD card */ + cdns_sdmmc_card_reset(); /* Enable Interrupt Flags*/ mmio_write_32((cdns_params.reg_base + SDHC_CDNS_SRS13), ~0); @@ -558,7 +555,7 @@ int cdns_send_cmd(struct mmc_cmd *cmd) timeout = TIMEOUT; do { udelay(100); - if (--timeout <= 0) { + if (--timeout == 0) { udelay(50); NOTICE("Timeout occur data and cmd line %x\n", mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09)); @@ -622,10 +619,42 @@ int cdns_send_cmd(struct mmc_cmd *cmd) timeout = TIMEOUT; + /* Wait for command completion or error */ do { udelay(CDNS_TIMEOUT); status = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12); - } while (((status & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0)); + if (--timeout == 0) { + ERROR("Command %u timeout waiting for response\n", + cmd->cmd_idx); + break; + } + } while (((status & (INT_CMD_DONE | ERROR_INT)) == 0)); + + /* For data commands, wait for Data Transfer Over (DTO) or data ready */ + if ((cmd_flags & DATA_PRESENT) != 0U) { + timeout = TIMEOUT; + do { + udelay(100); + status = mmio_read_32(cdns_params.reg_base + + SDHC_CDNS_SRS12); + if (--timeout == 0) { + ERROR("Command %u timeout waiting for data\n", + cmd->cmd_idx); + ERROR("SRS12=0x%08x SRS09=0x%08x\n", + mmio_read_32(cdns_params.reg_base + + SDHC_CDNS_SRS12), + mmio_read_32(cdns_params.reg_base + + SDHC_CDNS_SRS09)); + break; + } + /* + * In ADMA2 mode the controller raises Transfer Complete (bit 1) + * when the DMA finishes, TRAN_COMP. + */ + } while (((status & + (INT_DTO | INT_TXDR | INT_RXDR | TRAN_COMP)) == 0) && + ((status & ERROR_INT) == 0)); + } mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, (SRS_12_CC_EN)); status_check = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12) & 0xffff8000; @@ -735,17 +764,23 @@ int cdns_mmc_init(struct cdns_sdmmc_params *params, memcpy(&cdns_params, params, sizeof(struct cdns_sdmmc_params)); + /* + * Set device type before cdns_sd_host_init() so sdmmc_host_init() + * can branch between eMMC and SD card reset sequences. + */ + cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type; + cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); if (result < 0) { return result; } - cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type; cdns_params.cdn_sdmmc_dev_mode = SD_DS; + /* Select operating clock based on detected device type */ result = mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width, - params->flags, info); + params->flags, info); return result; } diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S index 4faa13abe..e9f7b1628 100644 --- a/include/arch/aarch32/asm_macros.S +++ b/include/arch/aarch32/asm_macros.S @@ -121,14 +121,6 @@ .endm #endif - /* Macro for error synchronization */ - .macro synchronize_errors - /* Complete any stores that may return an abort */ - dsb sy - /* Synchronise the CPU context with the completion of the dsb */ - isb - .endm - /* * Helper macro to generate the best mov/movw/movt combinations * according to the value to be moved. diff --git a/include/drivers/cadence/cdns_combo_phy.h b/include/drivers/cadence/cdns_combo_phy.h index 4d3a75394..8dddbee16 100644 --- a/include/drivers/cadence/cdns_combo_phy.h +++ b/include/drivers/cadence/cdns_combo_phy.h @@ -234,6 +234,5 @@ struct cdns_sdmmc_combo_phy { int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, uint32_t phy_reg_data, uint32_t phy_reg_data_value); int cdns_sd_card_detect(void); -int cdns_emmc_card_reset(void); #endif
\ No newline at end of file diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h index f4485ca8d..69ee5a1c9 100644 --- a/include/drivers/cadence/cdns_sdmmc.h +++ b/include/drivers/cadence/cdns_sdmmc.h @@ -12,6 +12,8 @@ #include <drivers/cadence/cdns_combo_phy.h> #include <drivers/mmc.h> +#include <platform_def.h> + #if MMC_DEVICE_TYPE == 0 #define CONFIG_DMA_ADDR_T_64BIT 0 #endif @@ -446,10 +448,16 @@ #define CONFIG_CDNS_DESC_COUNT 8 /* - * To accommodate SDMCLK set to 200MHz - * TODO: To support various clock range + * SD card, according to SD Host Controller Simplified Specification + * will be using High Speed default 50MHz as we have enabled HS mode. + * eMMC, according to JEDEC JESD84-B51, will be using legacy default + * 26MHz for max compatibility. */ +#if MMC_DEVICE_TYPE == 1 #define SDEMMC_SDCLK 50000000U +#else +#define SDEMMC_SDCLK 26000000U +#endif enum sd_opcode { SD_GO_IDLE_STATE = 0, diff --git a/lib/cpus/aarch64/c1_nano.S b/lib/cpus/aarch64/c1_nano.S index 26828ceb8..491f016c8 100644 --- a/lib/cpus/aarch64/c1_nano.S +++ b/lib/cpus/aarch64/c1_nano.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/107753/latest - * SDEN: https://developer.arm.com/documentation/SDEN-3273788/latest + * TRM: https://support.arm.com/documentation/107753/latest + * SDEN: https://support.arm.com/documentation/SDEN-3273788/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/c1_premium.S b/lib/cpus/aarch64/c1_premium.S index 4444574d1..06cf1fae5 100644 --- a/lib/cpus/aarch64/c1_premium.S +++ b/lib/cpus/aarch64/c1_premium.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/109416/latest - * SDEN: https://developer.arm.com/documentation/111078/latest + * TRM: https://support.arm.com/documentation/109416/latest + * SDEN: https://support.arm.com/documentation/111078/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/c1_pro.S b/lib/cpus/aarch64/c1_pro.S index 782e3cc4d..44b3c758e 100644 --- a/lib/cpus/aarch64/c1_pro.S +++ b/lib/cpus/aarch64/c1_pro.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/107771/latest - * SDEN: https://developer.arm.com/documentation/SDEN-3273080/latest + * TRM: https://support.arm.com/documentation/107771/latest + * SDEN: https://support.arm.com/documentation/SDEN-3273080/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/c1_ultra.S b/lib/cpus/aarch64/c1_ultra.S index fcef72e0f..2a1beea1e 100644 --- a/lib/cpus/aarch64/c1_ultra.S +++ b/lib/cpus/aarch64/c1_ultra.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/108014/latest - * SDEN: https://developer.arm.com/documentation/111077/latest + * TRM: https://support.arm.com/documentation/108014/latest + * SDEN: https://support.arm.com/documentation/111077/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a320.S b/lib/cpus/aarch64/cortex_a320.S index f5dad5459..21e4f7d87 100644 --- a/lib/cpus/aarch64/cortex_a320.S +++ b/lib/cpus/aarch64/cortex_a320.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/109551/latest - * SDEN: https://developer.arm.com/documentation/SDEN-2877630/latest + * TRM: https://support.arm.com/documentation/109551/latest + * SDEN: https://support.arm.com/documentation/SDEN-2877630/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S index cb560031e..7fc51853a 100644 --- a/lib/cpus/aarch64/cortex_a35.S +++ b/lib/cpus/aarch64/cortex_a35.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100236/latest - * SDEN: https://developer.arm.com/documentation/SDEN843627/latest + * TRM: https://support.arm.com/documentation/100236/latest + * SDEN: https://support.arm.com/documentation/SDEN843627/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index 491ee64cf..9813172ff 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101604/latest - * SDEN: https://developer.arm.com/documentation/SDEN1873351/latest + * TRM: https://support.arm.com/documentation/101604/latest + * SDEN: https://support.arm.com/documentation/SDEN1873351/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S index b62622e22..a0a65abcf 100644 --- a/lib/cpus/aarch64/cortex_a520.S +++ b/lib/cpus/aarch64/cortex_a520.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102517/latest - * SDEN: https://developer.arm.com/documentation/SDEN-2444153/latest + * TRM: https://support.arm.com/documentation/102517/latest + * SDEN: https://support.arm.com/documentation/SDEN-2444153/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a520ae.S b/lib/cpus/aarch64/cortex_a520ae.S index abc1a1e20..7af7a6c82 100644 --- a/lib/cpus/aarch64/cortex_a520ae.S +++ b/lib/cpus/aarch64/cortex_a520ae.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/107726/latest - * SDEN: https://developer.arm.com/documentation/SDEN-2343003/latest + * TRM: https://support.arm.com/documentation/107726/latest + * SDEN: https://support.arm.com/documentation/SDEN-2343003/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index ccda4c4d8..095c14611 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/ddi0500/latest - * SDEN: https://developer.arm.com/documentation/epm048406/latest + * TRM: https://support.arm.com/documentation/ddi0500/latest + * SDEN: https://support.arm.com/documentation/epm048406/latest */ #include <arch.h> #include <asm_macros.S> diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index 70b710719..30bc61703 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100442/latest - * SDEN: https://developer.arm.com/documentation/SDEN-859338/latest + * TRM: https://support.arm.com/documentation/100442/latest + * SDEN: https://support.arm.com/documentation/SDEN-859338/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index c386c7a9b..bdde84da9 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/ddi0488/latest - * SDEN: https://developer.arm.com/documentation/epm049219/latest + * TRM: https://support.arm.com/documentation/ddi0488/latest + * SDEN: https://support.arm.com/documentation/epm049219/latest */ #include <arch.h> #include <asm_macros.S> diff --git a/lib/cpus/aarch64/cortex_a65.S b/lib/cpus/aarch64/cortex_a65.S index 0eee1946c..650a4623b 100644 --- a/lib/cpus/aarch64/cortex_a65.S +++ b/lib/cpus/aarch64/cortex_a65.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100439/latest - * SDEN: https://developer.arm.com/documentation/SDEN1065159/latest/ + * TRM: https://support.arm.com/documentation/100439/latest + * SDEN: https://support.arm.com/documentation/SDEN1065159/latest/ */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S index fef56b8e2..ad6945004 100644 --- a/lib/cpus/aarch64/cortex_a65ae.S +++ b/lib/cpus/aarch64/cortex_a65ae.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101385/latest - * SDEN: https://developer.arm.com/documentation/SDEN1344564/latest + * TRM: https://support.arm.com/documentation/101385/latest + * SDEN: https://support.arm.com/documentation/SDEN1344564/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 7b430aea9..016f0b108 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101800/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1775101/latest + * TRM: https://support.arm.com/documentation/101800/latest + * SDEN: https://support.arm.com/documentation/SDEN-1775101/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index 4fcdb9cee..acf35607d 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101590/latest - * SDEN: https://developer.arm.com/documentation/SDEN2148827/latest + * TRM: https://support.arm.com/documentation/101590/latest + * SDEN: https://support.arm.com/documentation/SDEN2148827/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index 2effc666e..7b45e5989 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100095/latest - * SDEN: https://developer.arm.com/documentation/epm012079/latest + * TRM: https://support.arm.com/documentation/100095/latest + * SDEN: https://support.arm.com/documentation/epm012079/latest */ #include <arch.h> #include <asm_macros.S> diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S index a7c5ffe4e..f73ff3ea4 100644 --- a/lib/cpus/aarch64/cortex_a720.S +++ b/lib/cpus/aarch64/cortex_a720.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102530/latest - * SDEN: https://developer.arm.com/documentation/SDEN-2439421/latest + * TRM: https://support.arm.com/documentation/102530/latest + * SDEN: https://support.arm.com/documentation/SDEN-2439421/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a720ae.S b/lib/cpus/aarch64/cortex_a720ae.S index 7d96b3483..cfce9f9d4 100644 --- a/lib/cpus/aarch64/cortex_a720ae.S +++ b/lib/cpus/aarch64/cortex_a720ae.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102828/latest - * SDEN: https://developer.arm.com/documentation/SDEN-3090091/latest + * TRM: https://support.arm.com/documentation/102828/latest + * SDEN: https://support.arm.com/documentation/SDEN-3090091/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S index f1577c130..bf63bfa3a 100644 --- a/lib/cpus/aarch64/cortex_a725.S +++ b/lib/cpus/aarch64/cortex_a725.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/107652/latest - * SDEN: https://developer.arm.com/documentation/SDEN-2832921/latest + * TRM: https://support.arm.com/documentation/107652/latest + * SDEN: https://support.arm.com/documentation/SDEN-2832921/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S index 9d9d282aa..b309be19d 100644 --- a/lib/cpus/aarch64/cortex_a73.S +++ b/lib/cpus/aarch64/cortex_a73.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100048/latest - * SDEN: https://developer.arm.com/documentation/epm086451/latest + * TRM: https://support.arm.com/documentation/100048/latest + * SDEN: https://support.arm.com/documentation/epm086451/latest */ #include <arch.h> #include <asm_macros.S> diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index e24d5de85..be3dd17b7 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100403/latest - * SDEN: https://developer.arm.com/documentation/SDEN859515/latest + * TRM: https://support.arm.com/documentation/100403/latest + * SDEN: https://support.arm.com/documentation/SDEN859515/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 6d2619cfb..1b3b563e7 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100798/latest - * SDEN: https://developer.arm.com/documentation/SDEN-885749/latest + * TRM: https://support.arm.com/documentation/100798/latest + * SDEN: https://support.arm.com/documentation/SDEN-885749/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index 053579a02..14b8954a7 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101392/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1277541/latest + * TRM: https://support.arm.com/documentation/101392/latest + * SDEN: https://support.arm.com/documentation/SDEN-1277541/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index 24372b14c..2b5dec8e9 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101111/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1152370/latest + * TRM: https://support.arm.com/documentation/101111/latest + * SDEN: https://support.arm.com/documentation/SDEN-1152370/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 1f617bb53..6a014780f 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101430/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1401784/latest + * TRM: https://support.arm.com/documentation/101430/latest + * SDEN: https://support.arm.com/documentation/SDEN-1401784/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a78ae.S b/lib/cpus/aarch64/cortex_a78ae.S index cb63a8f36..d159a2bee 100644 --- a/lib/cpus/aarch64/cortex_a78ae.S +++ b/lib/cpus/aarch64/cortex_a78ae.S @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101779/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1707912/latest + * TRM: https://support.arm.com/documentation/101779/latest + * SDEN: https://support.arm.com/documentation/SDEN-1707912/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index 989675c77..dc0b9ec26 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102226/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1707916/latest + * TRM: https://support.arm.com/documentation/102226/latest + * SDEN: https://support.arm.com/documentation/SDEN-1707916/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S index 9ad9c5f66..1c011fc00 100644 --- a/lib/cpus/aarch64/cortex_x1.S +++ b/lib/cpus/aarch64/cortex_x1.S @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101433/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1401782/latest + * TRM: https://support.arm.com/documentation/101433/latest + * SDEN: https://support.arm.com/documentation/SDEN-1401782/latest */ #include <asm_macros.S> diff --git a/lib/cpus/aarch64/cortex_x1c.S b/lib/cpus/aarch64/cortex_x1c.S index 26d9baf7e..268852539 100644 --- a/lib/cpus/aarch64/cortex_x1c.S +++ b/lib/cpus/aarch64/cortex_x1c.S @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101968/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1707914/latest + * TRM: https://support.arm.com/documentation/101968/latest + * SDEN: https://support.arm.com/documentation/SDEN-1707914/latest */ #include <asm_macros.S> diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 1d6d5d08d..e89ebf96a 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101803/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1775100/latest + * TRM: https://support.arm.com/documentation/101803/latest + * SDEN: https://support.arm.com/documentation/SDEN-1775100/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 3333a54a0..8e0295bb3 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101593/latest - * SDEN: https://developer.arm.com/documentation/SDEN-2055130/latest + * TRM: https://support.arm.com/documentation/101593/latest + * SDEN: https://support.arm.com/documentation/SDEN-2055130/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S index da68caf63..3117630d7 100644 --- a/lib/cpus/aarch64/cortex_x4.S +++ b/lib/cpus/aarch64/cortex_x4.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102484/latest - * SDEN: https://developer.arm.com/documentation/109148/latest + * TRM: https://support.arm.com/documentation/102484/latest + * SDEN: https://support.arm.com/documentation/109148/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S index 3d1574246..6c477a10f 100644 --- a/lib/cpus/aarch64/cortex_x925.S +++ b/lib/cpus/aarch64/cortex_x925.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102807/latest - * SDEN: https://developer.arm.com/documentation/109180/latest/ + * TRM: https://support.arm.com/documentation/102807/latest + * SDEN: https://support.arm.com/documentation/109180/latest/ */ #include <arch.h> diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S index e38ebb9f9..335fff211 100644 --- a/lib/cpus/aarch64/neoverse_e1.S +++ b/lib/cpus/aarch64/neoverse_e1.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101560/latest - * SDEN: https://developer.arm.com/documentation/SDEN1402034/latest + * TRM: https://support.arm.com/documentation/101560/latest + * SDEN: https://support.arm.com/documentation/SDEN1402034/latest */ #include <arch.h> #include <asm_macros.S> diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 8019f35e4..545fb5f0c 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/100616/latest - * SDEN: https://developer.arm.com/documentation/SDEN-885747/latest + * TRM: https://support.arm.com/documentation/100616/latest + * SDEN: https://support.arm.com/documentation/SDEN-885747/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 249a393a0..9b09035e4 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102099/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1982442/latest + * TRM: https://support.arm.com/documentation/102099/latest + * SDEN: https://support.arm.com/documentation/SDEN-1982442/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/neoverse_n3.S b/lib/cpus/aarch64/neoverse_n3.S index 19a4c4236..632512350 100644 --- a/lib/cpus/aarch64/neoverse_n3.S +++ b/lib/cpus/aarch64/neoverse_n3.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/107997/latest - * SDEN: https://developer.arm.com/documentation/SDEN-3050973/latest + * TRM: https://support.arm.com/documentation/107997/latest + * SDEN: https://support.arm.com/documentation/SDEN-3050973/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 2509bdc1c..63b369082 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101427/latest - * SDEN: https://developer.arm.com/documentation/SDEN-1401781/latest + * TRM: https://support.arm.com/documentation/101427/latest + * SDEN: https://support.arm.com/documentation/SDEN-1401781/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index 314d4d2aa..599af6529 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/102375/latest - * SDEN: https://developer.arm.com/documentation/SDEN-2332927/latest + * TRM: https://support.arm.com/documentation/102375/latest + * SDEN: https://support.arm.com/documentation/SDEN-2332927/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S index 12f64621a..4ab3a3528 100644 --- a/lib/cpus/aarch64/neoverse_v3.S +++ b/lib/cpus/aarch64/neoverse_v3.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/107734/latest - * SDEN: https://developer.arm.com/documentation/109231/latest + * TRM: https://support.arm.com/documentation/107734/latest + * SDEN: https://support.arm.com/documentation/109231/latest */ #include <arch.h> diff --git a/lib/cpus/aarch64/neoverse_v3ae.S b/lib/cpus/aarch64/neoverse_v3ae.S index 06080cd7e..f5d8858f1 100644 --- a/lib/cpus/aarch64/neoverse_v3ae.S +++ b/lib/cpus/aarch64/neoverse_v3ae.S @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * TRM: https://developer.arm.com/documentation/101595/latest - * SDEN: https://developer.arm.com/documentation/109704/latest + * TRM: https://support.arm.com/documentation/101595/latest + * SDEN: https://support.arm.com/documentation/109704/latest */ #include <arch.h> diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c index c9145e687..e461810fa 100644 --- a/plat/intel/soc/common/soc/socfpga_reset_manager.c +++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c @@ -836,35 +836,23 @@ int socfpga_bridges_enable(uint32_t mask) return ret; } -int socfpga_bridge_nongraceful_disable(uint32_t mask) +int socfpga_bridge_nongraceful_disable(uint32_t f2s_force_drain, + uint32_t f2s_respempty) { int ret = 0; - int timeout = 1000; - uint32_t brg_mask = 0; - uint32_t f2s_idlereq = 0; - uint32_t f2s_force_drain = 0; - uint32_t f2s_en = 0; - uint32_t f2s_idleack = 0; - uint32_t f2s_respempty = 0; - uint32_t f2s_cmdidle = 0; - - socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq, - &f2s_force_drain, &f2s_en, - &f2s_idleack, &f2s_respempty, &f2s_cmdidle); - - mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), - f2s_idlereq); + int timeout = 300; + uint32_t idle_status = 0; /* Time out Error - Bus is still active */ /* Performing a non-graceful shutdown with Force drain */ mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), f2s_force_drain); + udelay(5); ret = -ETIMEDOUT; - do { - /* Read response queue status to ensure it is empty */ - uint32_t idle_status; + /* Read response queue status to ensure it is empty */ + do { idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0)); if ((idle_status & f2s_respempty) != 0U) { idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0)); @@ -875,7 +863,7 @@ int socfpga_bridge_nongraceful_disable(uint32_t mask) } } - asm("nop"); + udelay(1000); } while (timeout-- > 0); @@ -1188,7 +1176,8 @@ int socfpga_bridges_disable(uint32_t mask) f2s_en); udelay(5); - ret = socfpga_bridge_nongraceful_disable(mask); + ret = socfpga_bridge_nongraceful_disable(f2s_force_drain, + f2s_respempty); /* Bridge reset */ #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk index b0bbbc9ae..646503d6c 100644 --- a/plat/qemu/qemu_sbsa/platform.mk +++ b/plat/qemu/qemu_sbsa/platform.mk @@ -9,9 +9,6 @@ PLAT_QEMU_COMMON_PATH := plat/qemu/common CRASH_REPORTING := 1 -# Disable the PSCI platform compatibility layer -ENABLE_PLAT_COMPAT := 0 - SEPARATE_CODE_AND_RODATA := 1 ENABLE_STACK_PROTECTOR := 0 diff --git a/plat/qti/hoya/kodiak/sc7280_chrome/platform.mk b/plat/qti/hoya/kodiak/sc7280_chrome/platform.mk index 22a794c20..fa2d50b4c 100644 --- a/plat/qti/hoya/kodiak/sc7280_chrome/platform.mk +++ b/plat/qti/hoya/kodiak/sc7280_chrome/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -22,9 +22,6 @@ ERRATA_A78_1941498 := 1 ERRATA_A78_1951500 := 1 WORKAROUND_CVE_2025_10263 := 1 -# Disable the PSCI platform compatibility layer -ENABLE_PLAT_COMPAT := 0 - # Enable PSCI v1.0 extended state ID format PSCI_EXTENDED_STATE_ID := 1 ARM_RECOM_STATE_ID_ENC := 1 diff --git a/plat/qti/hoya/qcs615/platform.mk b/plat/qti/hoya/qcs615/platform.mk index 432a21e52..173cdc288 100644 --- a/plat/qti/hoya/qcs615/platform.mk +++ b/plat/qti/hoya/qcs615/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2024-2026, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2024, The Linux Foundation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -34,9 +34,6 @@ ERRATA_A76_1946160 := 1 ERRATA_A76_2743102 := 1 WORKAROUND_CVE_2025_10263 := 1 -# Disable the PSCI platform compatibility layer -ENABLE_PLAT_COMPAT := 0 - # Enable PSCI v1.0 extended state ID format PSCI_EXTENDED_STATE_ID := 1 ARM_RECOM_STATE_ID_ENC := 1 @@ -154,4 +151,3 @@ else # use library provided by QTISECLIB_PATH LDLIBS += $(QTISECLIB_PATH) endif - diff --git a/plat/qti/hoya/sc7180/platform.mk b/plat/qti/hoya/sc7180/platform.mk index 617e90692..442e8f213 100644 --- a/plat/qti/hoya/sc7180/platform.mk +++ b/plat/qti/hoya/sc7180/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -16,9 +16,6 @@ USE_COHERENT_MEM := 0 WARMBOOT_ENABLE_DCACHE_EARLY := 1 HW_ASSISTED_COHERENCY := 1 -# Disable the PSCI platform compatibility layer -ENABLE_PLAT_COMPAT := 0 - #Enable errata for cortex_a55 and cortex_a76 ERRATA_A55_1530923 := 1 ERRATA_A76_1165522 := 1 @@ -138,4 +135,3 @@ else # use library provided by QTISECLIB_PATH LDLIBS += $(QTISECLIB_PATH) endif - diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk index 2fdbec580..aaaec73c2 100644 --- a/plat/rockchip/px30/platform.mk +++ b/plat/rockchip/px30/platform.mk @@ -1,5 +1,5 @@ # -#Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. +#Copyright (c) 2019-2026, Arm Limited and Contributors. All rights reserved. # #SPDX-License-Identifier: BSD-3-Clause # @@ -63,8 +63,6 @@ ifdef PLAT_RK_SECURE_DDR_MINILOADER BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c endif -ENABLE_PLAT_COMPAT := 0 - include lib/libfdt/libfdt.mk PLAT_EXTRA_LD_SCRIPT := 1 diff --git a/plat/rockchip/rk3568/platform.mk b/plat/rockchip/rk3568/platform.mk index 1e130c7ee..8b49c7627 100644 --- a/plat/rockchip/rk3568/platform.mk +++ b/plat/rockchip/rk3568/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2023-2026, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -94,7 +94,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ ${RK_PLAT_SOC}/plat_sip_calls.c -ENABLE_PLAT_COMPAT := 0 MULTI_CONSOLE_API := 1 # System coherency is managed in hardware HW_ASSISTED_COHERENCY := 1 diff --git a/plat/rockchip/rk3576/platform.mk b/plat/rockchip/rk3576/platform.mk index da7eae136..9d33f8a03 100644 --- a/plat/rockchip/rk3576/platform.mk +++ b/plat/rockchip/rk3576/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2025, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2025-2026, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -101,7 +101,6 @@ ERRATA_A53_1530924 := 1 ERRATA_A72_1319367 := 1 -ENABLE_PLAT_COMPAT := 0 MULTI_CONSOLE_API := 1 CTX_INCLUDE_EL2_REGS := 0 CTX_INCLUDE_AARCH32_REGS := 0 diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk index 413a20c16..5c351f32f 100644 --- a/plat/rockchip/rk3588/platform.mk +++ b/plat/rockchip/rk3588/platform.mk @@ -81,7 +81,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/scmi/rk3588_rstd.c CTX_INCLUDE_AARCH32_REGS := 0 -ENABLE_PLAT_COMPAT := 0 MULTI_CONSOLE_API := 1 ERRATA_A55_1530923 := 1 WORKAROUND_CVE_2025_10263 := 1 diff --git a/plat/rockchip/rv1126b/platform.mk b/plat/rockchip/rv1126b/platform.mk index 41efa2422..ec8c1ea1b 100644 --- a/plat/rockchip/rv1126b/platform.mk +++ b/plat/rockchip/rv1126b/platform.mk @@ -99,7 +99,6 @@ ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 ERRATA_A53_1530924 := 1 -ENABLE_PLAT_COMPAT := 0 MULTI_CONSOLE_API := 1 CTX_INCLUDE_EL2_REGS := 0 CTX_INCLUDE_AARCH32_REGS := 0 diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c index b67e44296..c3ba06b0b 100644 --- a/plat/xilinx/common/pm_service/pm_ipi.c +++ b/plat/xilinx/common/pm_service/pm_ipi.c @@ -225,7 +225,8 @@ enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count) enum pm_ret_status ret = PM_RET_SUCCESS; if (count > (size_t)IPI_BUFFER_MAX_WORDS) { - return PM_RET_ERROR_ARGS; + ret = PM_RET_ERROR_ARGS; + goto exit_label; } for (i = 0; i < count; i++) { @@ -246,6 +247,7 @@ enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count) memset(value, 0, local_count); } #endif +exit_label: return ret; } |