From fcea95eb89cdf1ecb8ad806f935bbc8d316e34dd Mon Sep 17 00:00:00 2001 From: Xialin Liu Date: Wed, 31 Dec 2025 10:51:28 -0600 Subject: fix(cpus): workaround for Cortex-X3 erratum 3888125 Cortex-X3 erratum 3888125 that applies to revisions r0p0, r1p0, r1p1 and r1p2 of the CPU. It is still open. The erratum can be avoided by setting CPUACTLR2[22] to 1'b1, which will disable linking multiple Non-Cacheable or Device GRE loads to the same read request for the cache-line. This might have a significant performance impact to Non-cacheable and Device GRE read bandwidth for streaming scenarios. SDEN documentation: https://developer.arm.com/documentation/SDEN-2055130/latest Change-Id: I5c01dfcffc6e56163aba03428e21fedee8cc7042 Signed-off-by: Xialin Liu --- docs/design/cpu-specific-build-macros.rst | 6 +++++- lib/cpus/aarch64/cortex_x3.S | 8 +++++++- lib/cpus/cpu-ops.mk | 6 +++++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index c8141d883..0831c6c11 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -942,6 +942,10 @@ For Cortex-X3, the following errata build flags are defined : CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the CPU. It is fixed in r1p2. +- ``ERRATA_X3_3888125``: This applies errata 3888125 workaround to Cortex-X3 + CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 + of the CPU. It is still open. + For Cortex-X4, the following errata build flags are defined : - ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 @@ -1419,7 +1423,7 @@ GIC Errata Workarounds -------------- -*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2014-2026, Arm Limited and Contributors. All rights reserved.* .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 015715b53..261dc9b0a 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2025, Arm Limited. All rights reserved. + * Copyright (c) 2021-2026, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -118,6 +118,12 @@ workaround_reset_end cortex_x3, ERRATUM(3827463) check_erratum_ls cortex_x3, ERRATUM(3827463), CPU_REV(1, 1) +workaround_reset_start cortex_x3, ERRATUM(3888125), ERRATA_X3_3888125 + sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(22) +workaround_reset_end cortex_x3, ERRATUM(3888125) + +check_erratum_ls cortex_x3, ERRATUM(3888125), CPU_REV(1, 2) + workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 override_vector_table wa_cve_vbar_cortex_x3 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index ce8d0b0d6..34d0f2ea5 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2026, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -951,6 +951,10 @@ CPU_FLAG_LIST += ERRATA_X3_3692984 # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu. It is fixed in r1p2. CPU_FLAG_LIST += ERRATA_X3_3827463 +# Flag to apply erratum 3888125 workaround on reset. This erratum applies +# to revisions r0p0, r1p0, r1p1, r1p2 of the Cortex-X3 cpu and is still open. +CPU_FLAG_LIST += ERRATA_X3_3888125 + # Flag to apply erratum 2701112 workaround for platforms that do not use an # Arm interconnect IP. This erratum applies to revisions r0p0 of the Cortex-X4 # cpu and is fixed in r0p1. -- cgit v1.2.3 From 1c0c1b5467a8eca071962a532b6c69b30aa0482b Mon Sep 17 00:00:00 2001 From: Xialin Liu Date: Wed, 31 Dec 2025 10:54:42 -0600 Subject: fix(cpus): workaround for Cortex-X3 erratum 4302966 Cortex-X3 erratum 4302966 applies to revisions r0p0, r1p0, r1p1, r1p2, and it is still open. This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-2055130/latest Change-Id: I284ee7fe611c4c9861696fde62f796e6fae6dff6 Signed-off-by: Xialin Liu --- docs/design/cpu-specific-build-macros.rst | 4 ++++ lib/cpus/aarch64/cortex_x3.S | 6 ++++++ lib/cpus/cpu-ops.mk | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 0831c6c11..04a717c0d 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -946,6 +946,10 @@ For Cortex-X3, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the CPU. It is still open. +- ``ERRATA_X3_4302966``: This applies errata 4302966 workaround to Cortex-X3 + CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 + of the CPU. It is still open. + For Cortex-X4, the following errata build flags are defined : - ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 261dc9b0a..b89eb982b 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -124,6 +124,12 @@ workaround_reset_end cortex_x3, ERRATUM(3888125) check_erratum_ls cortex_x3, ERRATUM(3888125), CPU_REV(1, 2) +workaround_reset_start cortex_x3, ERRATUM(4302966), ERRATA_X3_4302966 + sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, BIT(50) +workaround_reset_end cortex_x3, ERRATUM(4302966) + +check_erratum_ls cortex_x3, ERRATUM(4302966), CPU_REV(1, 2) + workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 override_vector_table wa_cve_vbar_cortex_x3 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 34d0f2ea5..acde0af1b 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -955,6 +955,10 @@ CPU_FLAG_LIST += ERRATA_X3_3827463 # to revisions r0p0, r1p0, r1p1, r1p2 of the Cortex-X3 cpu and is still open. CPU_FLAG_LIST += ERRATA_X3_3888125 +# Flag to apply erratum 4302966 workaround on reset. This erratum applies +# to revisions r0p0, r1p0, r1p1, r1p2 of the Cortex-X3 cpu and is still open. +CPU_FLAG_LIST += ERRATA_X3_4302966 + # Flag to apply erratum 2701112 workaround for platforms that do not use an # Arm interconnect IP. This erratum applies to revisions r0p0 of the Cortex-X4 # cpu and is fixed in r0p1. -- cgit v1.2.3