Merge tag 'u-boot-imx-main-20260906' of https://git.u-boot-project.org/u-boot/custodians/u-boot-imx

CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-imx/-/pipelines/1190

- Fix EEPROM address on Data Modul i.MX8M Plus eDM SBC.
- Increase malloc area size on Data Modul i.MX8M eDM SBC.
- Reload the training firmware for every PHY configuration to avoid boot hang.

4 files changed, 15 insertions, 12 deletions

diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
index 6b40106e3bd..904c610b6de 100644
--- a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
@@ -296,9 +296,9 @@
 		self-powered;
 	};
 
-	eeprom: eeprom@50 {
+	eeprom: eeprom@51 {
 		compatible = "atmel,24c32";
-		reg = <0x50>;
+		reg = <0x51>;
 		pagesize = <32>;
 	};
 
diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config
index 18c7bb536fa..92940ddb947 100644
--- a/configs/imx8m_data_modul.config
+++ b/configs/imx8m_data_modul.config
@@ -196,7 +196,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
 CONFIG_SYS_EEPROM_SIZE=16384
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_ENV_MMC_EMMC_HW_PARTITION=1
 CONFIG_SYS_MONITOR_LEN=1048576
diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
index 1a2d071d6f1..63a6ca800a3 100644
--- a/drivers/ddr/imx/phy/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -12,6 +12,7 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
 {
 	struct dram_cfg_param *dram_cfg;
 	struct dram_fsp_msg *fsp_msg;
+	int last_fw_type = -1;
 	unsigned int num;
 	int i = 0;
 	int j = 0;
@@ -33,9 +34,18 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
 		/* set dram PHY input clocks to desired frequency */
 		ddrphy_init_set_dfi_clk(fsp_msg->drate);
 
-		/* load the dram training firmware image */
+		/*
+		 * Load the DRAM training firmware image, unless the same image has
+		 * already been loaded for an earlier frequency setpoint of this run.
+		 * It must be loaded again for every ddr_cfg_phy() call as the caller
+		 * resets the PHY before this, which leaves the image in the PHY memory
+		 * in an undefined state.
+		 */
 		dwc_ddrphy_apb_wr(0xd0000, 0x0);
-		ddr_load_train_firmware(fsp_msg->fw_type);
+		if (fsp_msg->fw_type != last_fw_type) {
+			ddr_load_train_firmware(fsp_msg->fw_type);
+			last_fw_type = fsp_msg->fw_type;
+		}
 
 		/* load the frequency set point message block parameter */
 		dram_cfg = fsp_msg->fsp_cfg;
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index 147ec9ab061..3c39c89de19 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -50,15 +50,8 @@ void ddr_load_train_firmware(enum fw_type type)
 	unsigned long imem_start = (unsigned long)_end + fw_offset;
 	unsigned long dmem_start;
 	unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
-	static enum fw_type last_type = -1;
 	unsigned long spl_start = 0;
 
-	/* If FW doesn't change, we can save the loading. */
-	if (last_type == type)
-		return;
-
-	last_type = type;
-
 #ifdef CONFIG_SPL_OF_CONTROL
 	if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
 		imem_start = roundup((unsigned long)_end +