Merge tag 'xilinx-for-v2026.10-rc4' of https://git.u-boot-project.org/u-boot/custodians/u-boot-amd

AMD/Xilinx fixes for v2026.10-rc3

AMD/Xilinx:
- MAINTAINERS fragment fixes

fpga:
- Check bitstream length against the supplied buffer

versal2:
- initialize num_banks variable in dram_init()
- move platform_id/platform_version to .data

versal-net:
- move platform_id/platform_version to .data

xilinx-spi:
- fix premature transfer termination at low SCK

11 files changed, 48 insertions, 17 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index e41ff7700df..79365697c23 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -805,7 +805,7 @@ N:	uniphier
 ARM VERSAL NET
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/mach-versal-net/
 F:	drivers/soc/soc_xilinx_versal_net.c
 N:	(?<!uni)versal-net
@@ -813,7 +813,7 @@ N:	(?<!uni)versal-net
 ARM VERSAL
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/mach-versal/
 F:	drivers/net/xilinx_axi_mrmac.*
 F:	drivers/soc/soc_xilinx_versal.c
@@ -824,7 +824,7 @@ N:	(?<!uni)versal
 ARM VERSAL GEN 2
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/mach-versal2/
 
 ARM VERSATILE EXPRESS DRIVERS
@@ -838,7 +838,7 @@ ARM ZYNQ and ZYNQMP
 M:	Michal Simek <monstr@monstr.eu>
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	doc/board/xilinx/
 F:	doc/device-tree-bindings/video/syncoam,seps525.txt
 F:	drivers/gpio/gpio_slg7xl45106.c
@@ -856,7 +856,7 @@ N:	zynq
 ARM ZYNQMP R5
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/mach-zynqmp-r5/
 
 ARM PHYTIUM
@@ -1125,7 +1125,7 @@ F:	test/dm/fastboot.c
 FPGA
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	drivers/fpga/
 F:	cmd/fpga.c
 F:	include/fpga.h
@@ -1274,7 +1274,7 @@ F:	lib/membuf.c
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/microblaze/
 F:	cmd/mfsl.c
 F:	drivers/gpio/xilinx_gpio.c
diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c
index 7df7c49ac71..1555751da2e 100644
--- a/arch/arm/mach-versal-net/cpu.c
+++ b/arch/arm/mach-versal-net/cpu.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2021 - 2022, Xilinx, Inc.
- * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -151,7 +151,8 @@ u8 __weak versal_net_get_bootmode(void)
 	return reg & BOOT_MODES_MASK;
 }
 
-static u32 platform_id, platform_version;
+static u32 platform_id __section(".data");
+static u32 platform_version __section(".data");
 
 char *soc_name_decode(void)
 {
diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c
index d72f66f4fba..19baa1331bd 100644
--- a/arch/arm/mach-versal2/cpu.c
+++ b/arch/arm/mach-versal2/cpu.c
@@ -241,7 +241,8 @@ void versal2_timer_setup(void)
 	debug("timer 0x%llx\n", get_ticks());
 }
 
-static u32 platform_id, platform_version;
+static u32 platform_id __section(".data");
+static u32 platform_version __section(".data");
 
 char *soc_name_decode(void)
 {
diff --git a/board/amd/versal2/MAINTAINERS b/board/amd/versal2/MAINTAINERS
index af7913d8db3..282eaddd753 100644
--- a/board/amd/versal2/MAINTAINERS
+++ b/board/amd/versal2/MAINTAINERS
@@ -1,7 +1,7 @@
 XILINX_VERSAL2 BOARDS
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/dts/versal2*
 F:	board/amd/
 F:	configs/amd*
diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c
index 15b79bbea69..ef6eb1af482 100644
--- a/board/amd/versal2/board.c
+++ b/board/amd/versal2/board.c
@@ -262,7 +262,8 @@ int dram_init(void)
 	ofnode mem = ofnode_null();
 	struct resource res;
 	int ret, i, reg = 0;
-	u32 num_banks, reloc_use = 0;
+	u32 num_banks = 0;
+	u32 reloc_use = 0;
 	u64 text = (u64)_start;
 
 	gd->ram_base = (unsigned long)~0;
diff --git a/board/xilinx/versal-net/MAINTAINERS b/board/xilinx/versal-net/MAINTAINERS
index 50120a88d6e..85d858ad3a0 100644
--- a/board/xilinx/versal-net/MAINTAINERS
+++ b/board/xilinx/versal-net/MAINTAINERS
@@ -1,7 +1,7 @@
 XILINX_VERSAL_NET BOARDS
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/dts/versal-net*
 F:	board/xilinx/versal-net/
 F:	include/configs/xilinx_versal_net*
diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS
index 07173ee916f..00170a9cf66 100644
--- a/board/xilinx/versal/MAINTAINERS
+++ b/board/xilinx/versal/MAINTAINERS
@@ -1,7 +1,7 @@
 XILINX_VERSAL BOARDS
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/dts/versal*
 F:	board/xilinx/versal/
 F:	include/configs/xilinx_versal*
diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
index 3eb1a451b58..d505a78ba66 100644
--- a/board/xilinx/zynq/MAINTAINERS
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -1,7 +1,7 @@
 ZYNQ BOARD
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/dts/zynq-*
 F:	board/xilinx/zynq/
 F:	include/configs/zynq*.h
diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 3db240782f4..8bc50e37e48 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -1,7 +1,7 @@
 XILINX_ZYNQMP BOARDS
 M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
-T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git
+T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-amd.git
 F:	arch/arm/dts/zynqmp-*
 F:	arch/arm/dts/avnet-ultra96*
 F:	board/xilinx/common/
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index b6966c7d2cb..c0f8e61f9bf 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -44,6 +44,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
 	unsigned int length;
 	unsigned int swapsize;
 	unsigned char *dataptr;
+	unsigned long hdrlen;
 	unsigned int i;
 	const fpga_desc *desc;
 	xilinx_desc *xdesc;
@@ -143,6 +144,14 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
 	dataptr += 4;
 	printf("  bytes in bitstream = %d\n", swapsize);
 
+	/* Make sure the header and data fit in the caller's buffer */
+	hdrlen = (unsigned long)dataptr - (unsigned long)fpgadata;
+	if (hdrlen > size || swapsize > size - hdrlen) {
+		printf("%s: Bitstream does not fit in %lu byte buffer\n",
+		       __func__, (unsigned long)size);
+		return FPGA_FAIL;
+	}
+
 	return fpga_load(devnum, dataptr, swapsize, bstype, 0);
 }
 
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index b2af17ebae9..011bbc93076 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -53,6 +53,8 @@
 #define SPISR_RX_FULL		BIT(1)
 #define SPISR_RX_EMPTY		BIT(0)
 
+#define IPISR_DTR_EMPTY		BIT(2)
+
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
 #define SPIDTR_8BIT_MASK	GENMASK(7, 0)
 #define SPIDTR_16BIT_MASK	GENMASK(15, 0)
@@ -256,6 +258,13 @@ static int start_transfer(struct udevice *dev, const void *dout, void *din, u32
 		reg = readl(&regs->spicr) | SPICR_MASTER_INHIBIT;
 		writel(reg, &regs->spicr);
 		count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+		/*
+		 * Clear any stale DTR_EMPTY before starting. IPISR is
+		 * toggle-on-write, so only write (toggle) the bit when it is
+		 * actually set, otherwise the write would spuriously set it.
+		 */
+		if (readl(&regs->ipisr) & IPISR_DTR_EMPTY)
+			writel(IPISR_DTR_EMPTY, &regs->ipisr);
 		/* Enable master transaction */
 		reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
 		writel(reg, &regs->spicr);
@@ -263,12 +272,22 @@ static int start_transfer(struct udevice *dev, const void *dout, void *din, u32
 		if (txp)
 			txp += count;
 
-		ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,
+		/*
+		 * Wait for the transfer to fully complete before inhibiting
+		 * the master. The final byte may still be in the shift
+		 * pipeline. Poll IPISR_DTR_EMPTY, which is set only once the
+		 * last byte has been shifted out to the slave. Asserting
+		 * MASTER_INHIBIT before this stops SCK and truncates the last
+		 * byte, which is observable at low SCK frequencies.
+		 */
+		ret = wait_for_bit_le32(&regs->ipisr, IPISR_DTR_EMPTY, true,
 					XILINX_SPISR_TIMEOUT, false);
 		if (ret < 0) {
 			printf("XILSPI error: Xfer timeout\n");
 			return ret;
 		}
+		/* IPISR is toggle-on-write; write 1 to clear DTR_EMPTY */
+		writel(IPISR_DTR_EMPTY, &regs->ipisr);
 
 		reg = readl(&regs->spicr) | SPICR_MASTER_INHIBIT;
 		writel(reg, &regs->spicr);