Merge tag 'mediatek-for-next-2026-09-02' of https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek into next

* New mipi_dsi_{generic,dcs}_write_seq() helper macros
* Convert 5 panel drivers to use the new mipi_dsi write_seq macros
* Support num-interpolated-steps in pwm_backlight
* Fix MediaTek clock driver using BSS before relocation
* New MT8366 clock driver and dt-bindings clock header
* MediaTek power domain: bus_prot_sta_mask field and BUS_PROT_WR_IGN() macros
* New MT8366 power domain support and dt-bindings header
* Fix setting DCM_TOP_EN on chips that don't have it in MediaTek power domain driver
* Devicetree cleanups: drop mt8188 tphy fallback, remove unused mt6357.dtsi
* Remove UFS defconfigs for Genio EVKs

29 files changed, 2824 insertions, 689 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 7ced7f9aaec..2b3a9ac1f2a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1264,6 +1264,7 @@ F:	include/configs/mt7621.h
 F:	include/dt-bindings/clock/mt7620-clk.h
 F:	include/dt-bindings/clock/mt7621-clk.h
 F:	include/dt-bindings/clock/mt7628-clk.h
+F:	include/dt-bindings/clock/mt8366-clk.h
 F:	include/dt-bindings/reset/mt7620-reset.h
 F:	include/dt-bindings/reset/mt7621-reset.h
 F:	include/dt-bindings/reset/mt7628-reset.h
diff --git a/arch/arm/dts/mt6357.dtsi b/arch/arm/dts/mt6357.dtsi
deleted file mode 100644
index 3330a03c2f7..00000000000
--- a/arch/arm/dts/mt6357.dtsi
+++ /dev/null
@@ -1,282 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Copyright (c) 2023 BayLibre Inc.
- */
-
-#include <dt-bindings/input/input.h>
-
-&pwrap {
-	mt6357_pmic: pmic {
-		compatible = "mediatek,mt6357";
-
-		regulators {
-			mt6357_vproc_reg: buck-vproc {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <518750>;
-				regulator-max-microvolt = <1312500>;
-				regulator-ramp-delay = <6250>;
-				regulator-enable-ramp-delay = <220>;
-				regulator-always-on;
-			};
-
-			mt6357_vcore_reg: buck-vcore {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <518750>;
-				regulator-max-microvolt = <1312500>;
-				regulator-ramp-delay = <6250>;
-				regulator-enable-ramp-delay = <220>;
-				regulator-always-on;
-			};
-
-			mt6357_vmodem_reg: buck-vmodem {
-				regulator-name = "vmodem";
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1193750>;
-				regulator-ramp-delay = <6250>;
-				regulator-enable-ramp-delay = <220>;
-			};
-
-			mt6357_vs1_reg: buck-vs1 {
-				regulator-name = "vs1";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <2200000>;
-				regulator-ramp-delay = <12500>;
-				regulator-enable-ramp-delay = <220>;
-				regulator-always-on;
-			};
-
-			mt6357_vpa_reg: buck-vpa {
-				regulator-name = "vpa";
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <3650000>;
-				regulator-ramp-delay = <50000>;
-				regulator-enable-ramp-delay = <220>;
-			};
-
-			mt6357_vfe28_reg: ldo-vfe28 {
-				compatible = "regulator-fixed";
-				regulator-name = "vfe28";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vxo22_reg: ldo-vxo22 {
-				regulator-name = "vxo22";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <2400000>;
-				regulator-enable-ramp-delay = <110>;
-			};
-
-			mt6357_vrf18_reg: ldo-vrf18 {
-				compatible = "regulator-fixed";
-				regulator-name = "vrf18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-enable-ramp-delay = <110>;
-			};
-
-			mt6357_vrf12_reg: ldo-vrf12 {
-				compatible = "regulator-fixed";
-				regulator-name = "vrf12";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-enable-ramp-delay = <110>;
-			};
-
-			mt6357_vefuse_reg: ldo-vefuse {
-				regulator-name = "vefuse";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vcn33_bt_reg: ldo-vcn33-bt {
-				regulator-name = "vcn33-bt";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3500000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
-				regulator-name = "vcn33-wifi";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3500000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vcn28_reg: ldo-vcn28 {
-				compatible = "regulator-fixed";
-				regulator-name = "vcn28";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vcn18_reg: ldo-vcn18 {
-				compatible = "regulator-fixed";
-				regulator-name = "vcn18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vcama_reg: ldo-vcama {
-				regulator-name = "vcama";
-				regulator-min-microvolt = <2500000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vcamd_reg: ldo-vcamd {
-				regulator-name = "vcamd";
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vcamio_reg: ldo-vcamio18 {
-				compatible = "regulator-fixed";
-				regulator-name = "vcamio";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vldo28_reg: ldo-vldo28 {
-				regulator-name = "vldo28";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vsram_others_reg: ldo-vsram-others {
-				regulator-name = "vsram-others";
-				regulator-min-microvolt = <518750>;
-				regulator-max-microvolt = <1312500>;
-				regulator-ramp-delay = <6250>;
-				regulator-enable-ramp-delay = <110>;
-				regulator-always-on;
-			};
-
-			mt6357_vsram_proc_reg: ldo-vsram-proc {
-				regulator-name = "vsram-proc";
-				regulator-min-microvolt = <518750>;
-				regulator-max-microvolt = <1312500>;
-				regulator-ramp-delay = <6250>;
-				regulator-enable-ramp-delay = <110>;
-				regulator-always-on;
-			};
-
-			mt6357_vaux18_reg: ldo-vaux18 {
-				compatible = "regulator-fixed";
-				regulator-name = "vaux18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vaud28_reg: ldo-vaud28 {
-				compatible = "regulator-fixed";
-				regulator-name = "vaud28";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vio28_reg: ldo-vio28 {
-				compatible = "regulator-fixed";
-				regulator-name = "vio28";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vio18_reg: ldo-vio18 {
-				compatible = "regulator-fixed";
-				regulator-name = "vio18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-enable-ramp-delay = <264>;
-				regulator-always-on;
-			};
-
-			mt6357_vdram_reg: ldo-vdram {
-				regulator-name = "vdram";
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-enable-ramp-delay = <3300>;
-			};
-
-			mt6357_vmc_reg: ldo-vmc {
-				regulator-name = "vmc";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-enable-ramp-delay = <44>;
-			};
-
-			mt6357_vmch_reg: ldo-vmch {
-				regulator-name = "vmch";
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-enable-ramp-delay = <44>;
-			};
-
-			mt6357_vemc_reg: ldo-vemc {
-				regulator-name = "vemc";
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-enable-ramp-delay = <44>;
-				regulator-always-on;
-			};
-
-			mt6357_vsim1_reg: ldo-vsim1 {
-				regulator-name = "vsim1";
-				regulator-min-microvolt = <1700000>;
-				regulator-max-microvolt = <3100000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vsim2_reg: ldo-vsim2 {
-				regulator-name = "vsim2";
-				regulator-min-microvolt = <1700000>;
-				regulator-max-microvolt = <3100000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-
-			mt6357_vibr_reg: ldo-vibr {
-				regulator-name = "vibr";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-enable-ramp-delay = <44>;
-			};
-
-			mt6357_vusb33_reg: ldo-vusb33 {
-				regulator-name = "vusb33";
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3100000>;
-				regulator-enable-ramp-delay = <264>;
-			};
-		};
-
-		rtc {
-			compatible = "mediatek,mt6357-rtc";
-		};
-
-		keys {
-			compatible = "mediatek,mt6357-keys";
-
-			key-power {
-				linux,keycodes = <KEY_POWER>;
-				wakeup-source;
-			};
-
-			key-home {
-				linux,keycodes = <KEY_HOME>;
-				wakeup-source;
-			};
-
-		};
-	};
-};
diff --git a/arch/arm/dts/mt8188-u-boot.dtsi b/arch/arm/dts/mt8188-u-boot.dtsi
deleted file mode 100644
index 6d1b2ab82da..00000000000
--- a/arch/arm/dts/mt8188-u-boot.dtsi
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2025 Baylibre SAS.
- * Author: Julien Masson <jmasson@baylibre.com>
- */
-
-&u3phy0 {
-	compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3",
-		     "mediatek,generic-tphy-v2";
-};
diff --git a/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi b/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi
deleted file mode 100644
index 586d15bf72e..00000000000
--- a/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2026 BayLibre, SAS.
- * Author: Julien Stephan <jstephan@baylibre.com>
- */
-
-#include "mt8188-u-boot.dtsi"
diff --git a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi
deleted file mode 100644
index 586d15bf72e..00000000000
--- a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2026 BayLibre, SAS.
- * Author: Julien Stephan <jstephan@baylibre.com>
- */
-
-#include "mt8188-u-boot.dtsi"
diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS
index d99c6d708b2..47f91d6e81c 100644
--- a/board/mediatek/MAINTAINERS
+++ b/board/mediatek/MAINTAINERS
@@ -5,12 +5,9 @@ F:	arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi
 F:	arch/arm/dts/mt8371-genio-common-u-boot.dtsi
 F:	arch/arm/dts/mt8371-genio-common-ufs.dtso
 F:	arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi
-F:	configs/mt8189-ufs.config
 F:	configs/mt8189.config
 F:	configs/mt8371_genio_520_evk_defconfig
-F:	configs/mt8371_genio_520_evk_ufs_defconfig
 F:	configs/mt8391_genio_720_evk_defconfig
-F:	configs/mt8391_genio_720_evk_ufs_defconfig
 
 MT8365 EVK
 M:	Julien Masson <jmasson@baylibre.com>
@@ -34,4 +31,3 @@ M:	Julien Stephan <jstephan@baylibre.com>
 S:	Maintained
 F:	configs/mt8195.config
 F:	configs/mt8395_genio_1200_evk_defconfig
-F:	configs/mt8395_genio_1200_evk_ufs_defconfig
diff --git a/configs/mt8189-ufs.config b/configs/mt8189-ufs.config
deleted file mode 100644
index 8a7afb95b1b..00000000000
--- a/configs/mt8189-ufs.config
+++ /dev/null
@@ -1,8 +0,0 @@
-#include <configs/mt8189.config>
-
-CONFIG_PHY=y
-CONFIG_PHY_MTK_UFS=y
-CONFIG_SCSI=y
-CONFIG_UFS=y
-CONFIG_UFS_MEDIATEK=y
-CONFIG_CMD_UFS=y
diff --git a/configs/mt8189.config b/configs/mt8189.config
index 7c37c37a199..bc662811ade 100644
--- a/configs/mt8189.config
+++ b/configs/mt8189.config
@@ -16,6 +16,7 @@ CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -40,6 +41,7 @@ CONFIG_DM_PMIC_MTK_PWRAP=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_MT6359=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=921600
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
@@ -49,5 +51,7 @@ CONFIG_MTK_SNOR=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_MTK=y
+CONFIG_UFS=y
+CONFIG_UFS_MEDIATEK=y
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
diff --git a/configs/mt8195.config b/configs/mt8195.config
index c12ff93e3eb..885ba2d157c 100644
--- a/configs/mt8195.config
+++ b/configs/mt8195.config
@@ -13,16 +13,21 @@ CONFIG_BOOTSTD_FULL=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_UFS=y
 CONFIG_OF_UPSTREAM=y
 CONFIG_CLK=y
 CONFIG_MMC_MTK=y
+CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_MTK_PWRAP=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_MT6359=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=921600
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
+CONFIG_UFS=y
+CONFIG_UFS_MEDIATEK=y
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
diff --git a/configs/mt8371_genio_520_evk_ufs_defconfig b/configs/mt8371_genio_520_evk_ufs_defconfig
deleted file mode 100644
index a0b365a86a2..00000000000
--- a/configs/mt8371_genio_520_evk_ufs_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/mt8189-ufs.config>
-
-CONFIG_DEFAULT_DEVICE_TREE="mt8371-genio-520-evk-ufs"
-CONFIG_DEFAULT_FDT_FILE="mt8371-genio-520-evk-ufs"
diff --git a/configs/mt8391_genio_720_evk_ufs_defconfig b/configs/mt8391_genio_720_evk_ufs_defconfig
deleted file mode 100644
index f1de9d5fa1e..00000000000
--- a/configs/mt8391_genio_720_evk_ufs_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/mt8189-ufs.config>
-
-CONFIG_DEFAULT_DEVICE_TREE="mt8391-genio-720-evk-ufs"
-CONFIG_DEFAULT_FDT_FILE="mt8391-genio-720-evk-ufs"
diff --git a/configs/mt8395_genio_1200_evk_ufs_defconfig b/configs/mt8395_genio_1200_evk_ufs_defconfig
deleted file mode 100644
index 525638f5800..00000000000
--- a/configs/mt8395_genio_1200_evk_ufs_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-#include <configs/mt8195.config>
-
-CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8395-genio-1200-evk-ufs"
-CONFIG_CMD_UFS=y
-CONFIG_PHY=y
-CONFIG_SCSI=y
-CONFIG_UFS=y
-CONFIG_UFS_MEDIATEK=y
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index d4cac6aaf52..00ebb50ae6f 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_TARGET_MT8188) += clk-mt8188.o
 obj-$(CONFIG_TARGET_MT8189) += clk-mt8189.o
 obj-$(CONFIG_TARGET_MT8195) += clk-mt8195.o
 obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o
+obj-$(CONFIG_TARGET_MT8366) += clk-mt8366.o
 obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o
 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8366.c b/drivers/clk/mediatek/clk-mt8366.c
new file mode 100644
index 00000000000..533b769324c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8366.c
@@ -0,0 +1,1561 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 BayLibre, SAS
+ * Copyright (c) 2026 MediaTek Inc.
+ * Author: Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Author: David Lechner <dlechner@baylibre.com>
+ */
+
+#include <dm.h>
+#include <dt-bindings/clock/mt8366-clk.h>
+#include <linux/kernel.h>
+#include "clk-mtk.h"
+
+enum {
+	CLK_PAD_CLK32K,
+	CLK_PAD_CLK26M,
+	CLK_PAD_CLK13M,
+	CLK_PAD_ULPOSC,
+	CLK_PAD_ANA_LVDS,
+};
+
+static const ulong ext_clock_rates[] = {
+	[CLK_PAD_CLK32K] = 32000,
+	[CLK_PAD_CLK26M] = 26 * MHZ,
+	[CLK_PAD_CLK13M] = 13 * MHZ,
+	[CLK_PAD_ULPOSC] = 260 * MHZ,
+	[CLK_PAD_ANA_LVDS] = 118.9 * MHZ,
+};
+
+#define MT8366_PLL_FMAX		(3800UL * MHZ)
+#define MT8366_PLL_FMIN		(1500UL * MHZ)
+#define MT8366_INTEGER_BITS	8
+
+#define PLL(_id, _reg, _flags, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift, \
+	    _pcwbits)                                                    \
+	{                                                                \
+		.id = _id,                                               \
+		.reg = _reg,                                             \
+		.flags = (_flags),                                       \
+		.fmax = MT8366_PLL_FMAX,                                 \
+		.fmin = MT8366_PLL_FMIN,                                 \
+		.pd_reg = _pd_reg,                                       \
+		.pd_shift = _pd_shift,                                   \
+		.pcw_reg = _pcw_reg,                                     \
+		.pcw_shift = _pcw_shift,                                 \
+		.pcwbits = _pcwbits,                                     \
+		.pcwibits = MT8366_INTEGER_BITS,                         \
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL_LL, 0x304, 0, 0x308, 24, 0x308, 0, 22),
+	PLL(CLK_APMIXED_ARMPLL_BL, 0x314, 0, 0x318, 24, 0x318, 0, 22),
+	PLL(CLK_APMIXED_CCIPLL, 0x324, 0, 0x328, 24, 0x328, 0, 22),
+	PLL(CLK_APMIXED_APLL1, 0x204, 0, 0x208, 24, 0x20c, 0, 32),
+	PLL(CLK_APMIXED_APLL2, 0x218, 0, 0x21c, 24, 0x220, 0, 32),
+	PLL(CLK_APMIXED_APLL3, 0x700, 0, 0x704, 24, 0x708, 0, 32),
+	PLL(CLK_APMIXED_APLL4, 0x714, 0, 0x718, 24, 0x71c, 0, 32),
+	PLL(CLK_APMIXED_APLL5, 0x728, 0, 0x72c, 24, 0x730, 0, 32),
+	PLL(CLK_APMIXED_MAINPLL, 0x424, 0, 0x428, 24, 0x428, 0, 22),
+	PLL(CLK_APMIXED_UNIVPLL, 0x434, 0, 0x438, 24, 0x438, 0, 22),
+	PLL(CLK_APMIXED_MMPLL, 0x604, 0, 0x608, 24, 0x608, 0, 22),
+	PLL(CLK_APMIXED_TVDPLL1, 0x614, 0, 0x618, 24, 0x618, 0, 22),
+	PLL(CLK_APMIXED_TVDPLL2, 0x624, 0, 0x628, 24, 0x628, 0, 22),
+	PLL(CLK_APMIXED_MSDCPLL, 0x634, 0, 0x638, 24, 0x638, 0, 22),
+	PLL(CLK_APMIXED_MFGPLL, 0x504, 0, 0x508, 24, 0x508, 0, 22),
+	PLL(CLK_APMIXED_APUPLL2, 0x414, 0, 0x418, 24, 0x418, 0, 22),
+	PLL(CLK_APMIXED_APUPLL, 0x404, 0, 0x408, 24, 0x408, 0, 22),
+	PLL(CLK_APMIXED_ETHPLL, 0x514, 0, 0x518, 24, 0x518, 0, 22),
+	PLL(CLK_APMIXED_CANPLL, 0x524, 0, 0x528, 24, 0x528, 0, 22),
+	PLL(CLK_APMIXED_EMIPLL, 0x534, 0, 0x538, 24, 0x538, 0, 22),
+};
+
+static const struct mtk_clk_tree mt8366_apmixed_tree = {
+	.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.plls = apmixed_plls,
+	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+	FACTOR(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D4_D2, CLK_APMIXED_MAINPLL, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D4_D4, CLK_APMIXED_MAINPLL, 1, 16, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D4_D8, CLK_APMIXED_MAINPLL, 43, 1375, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D5_D2, CLK_APMIXED_MAINPLL, 1, 10, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D6_D2, CLK_APMIXED_MAINPLL, 1, 12, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D6_D4, CLK_APMIXED_MAINPLL, 1, 24, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D7_D2, CLK_APMIXED_MAINPLL, 1, 14, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D7_D4, CLK_APMIXED_MAINPLL, 1, 28, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D7_D8, CLK_APMIXED_MAINPLL, 1, 56, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D2, CLK_APMIXED_UNIVPLL, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D4, CLK_APMIXED_UNIVPLL, 1, 16, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D8, CLK_APMIXED_UNIVPLL, 1, 32, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_APMIXED_UNIVPLL, 1, 10, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_APMIXED_UNIVPLL, 1, 20, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D8, CLK_APMIXED_UNIVPLL, 1, 40, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D2, CLK_APMIXED_UNIVPLL, 1, 12, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D4, CLK_APMIXED_UNIVPLL, 1, 24, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D8, CLK_APMIXED_UNIVPLL, 1, 48, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D16, CLK_APMIXED_UNIVPLL, 1, 96, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D7_D2, CLK_APMIXED_UNIVPLL, 1, 14, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D7_D3, CLK_APMIXED_UNIVPLL, 1, 21, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D2, CLK_APMIXED_UNIVPLL, 1, 26, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D4, CLK_APMIXED_UNIVPLL, 1, 52, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D8, CLK_APMIXED_UNIVPLL, 1, 104, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D16, CLK_APMIXED_UNIVPLL, 1, 208, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D32, CLK_APMIXED_UNIVPLL, 1, 416, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D10, CLK_APMIXED_UNIVPLL, 1, 130, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D4_D2, CLK_APMIXED_MMPLL, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D4_D4, CLK_APMIXED_MMPLL, 1, 16, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D5_D2, CLK_APMIXED_MMPLL, 1, 10, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D6_D2, CLK_APMIXED_MMPLL, 1, 12, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 31, 495, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_CANPLL_D5, CLK_APMIXED_CANPLL, 1, 5, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_CANPLL_D10, CLK_APMIXED_CANPLL, 1, 10, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_CANPLL_D20, CLK_APMIXED_CANPLL, 1, 20, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_CANPLL_D25, CLK_APMIXED_CANPLL, 1, 25, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_OSC_D2, CLK_PAD_ULPOSC, 1, 2, CLK_PARENT_EXT),
+	FACTOR(CLK_TOP_OSC_D4, CLK_PAD_ULPOSC, 1, 4, CLK_PARENT_EXT),
+	FACTOR(CLK_TOP_OSC_D8, CLK_PAD_ULPOSC, 1, 8, CLK_PARENT_EXT),
+	FACTOR(CLK_TOP_OSC_D16, CLK_PAD_ULPOSC, 61, 973, CLK_PARENT_EXT),
+	FACTOR(CLK_TOP_OSC_D10, CLK_PAD_ULPOSC, 1, 10, CLK_PARENT_EXT),
+	FACTOR(CLK_TOP_OSC_D20, CLK_PAD_ULPOSC, 1, 20, CLK_PARENT_EXT),
+};
+
+static const struct mtk_parent kp_irq_gen_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D4),
+};
+
+static const struct mtk_parent lvdstx_clkdig_cts_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	EXT_PARENT(CLK_PAD_ANA_LVDS),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3),
+};
+
+static const struct mtk_parent uart_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8),
+};
+
+static const struct mtk_parent spm_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D10),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D4),
+	EXT_PARENT(CLK_PAD_CLK32K),
+};
+
+static const struct mtk_parent bus_aximem_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+};
+
+static const struct mtk_parent mcupm_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+};
+
+static const struct mtk_parent msdc5hclk_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+};
+
+static const struct mtk_parent pcie_mac_tl_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+};
+
+static const struct mtk_parent msdc_macro_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	APMIXED_PARENT(CLK_APMIXED_MSDCPLL),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+};
+
+static const struct mtk_parent pwm_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D10),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8),
+};
+
+static const struct mtk_parent usb_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+};
+
+static const struct mtk_parent snps_eth_250m_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_ETHPLL_D2),
+};
+
+static const struct mtk_parent snps_eth_50m_rmii_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_ETHPLL_D10),
+};
+
+static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_ETHPLL_D8),
+	TOP_PARENT(CLK_TOP_APLL1_D3),
+	TOP_PARENT(CLK_TOP_APLL2_D3),
+};
+
+static const struct mtk_parent dsi_occ_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+};
+
+static const struct mtk_parent camtm_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D7),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+};
+
+static const struct mtk_parent camtg_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8),
+	TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16),
+	EXT_PARENT(CLK_PAD_CLK13M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D8),
+	TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10),
+	TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32),
+};
+
+static const struct mtk_parent msdc30_1_h_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MSDCPLL_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+};
+
+static const struct mtk_parent msdc30_2_h_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MSDCPLL_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+};
+
+static const struct mtk_parent pwrap_ulposc_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D10),
+	TOP_PARENT(CLK_TOP_OSC_D8),
+	TOP_PARENT(CLK_TOP_OSC_D16),
+};
+
+static const struct mtk_parent can0_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_CANPLL_D5),
+	TOP_PARENT(CLK_TOP_CANPLL_D10),
+	TOP_PARENT(CLK_TOP_CANPLL_D20),
+	TOP_PARENT(CLK_TOP_CANPLL_D25),
+};
+
+static const struct mtk_parent mfg_ref_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+};
+
+static const struct mtk_parent aud_intbus_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D4),
+};
+
+static const struct mtk_parent vadsp_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D20),
+	TOP_PARENT(CLK_TOP_OSC_D10),
+	TOP_PARENT(CLK_TOP_OSC_D2),
+	EXT_PARENT(CLK_PAD_ULPOSC),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+};
+
+static const struct mtk_parent oscd10_26m_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent mdp_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	APMIXED_PARENT(CLK_APMIXED_TVDPLL2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+	TOP_PARENT(CLK_TOP_MMPLL_D5_D2),
+};
+
+static const struct mtk_parent img1_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+	TOP_PARENT(CLK_TOP_MMPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_MMPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D5_D2),
+};
+
+static const struct mtk_parent ipe_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	TOP_PARENT(CLK_TOP_MMPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D5_D2),
+};
+
+static const struct mtk_parent cam_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	TOP_PARENT(CLK_TOP_MMPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MMPLL_D7),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+};
+
+static const struct mtk_parent vdec_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_192M_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D7),
+	TOP_PARENT(CLK_TOP_MMPLL_D7),
+	TOP_PARENT(CLK_TOP_MMPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+};
+
+static const struct mtk_parent venc_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MMPLL_D7),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MMPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5),
+};
+
+static const struct mtk_parent i2cp_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D8),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+};
+
+static const struct mtk_parent seninf_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D7),
+	TOP_PARENT(CLK_TOP_MMPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+};
+
+static const struct mtk_parent msdc30_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MSDCPLL_D2),
+};
+
+static const struct mtk_parent aes_msdcfbe_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+};
+
+static const struct mtk_parent sspm_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D9),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+};
+
+static const struct mtk_parent disp_pwm_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_OSC_D2),
+	TOP_PARENT(CLK_TOP_OSC_D4),
+	TOP_PARENT(CLK_TOP_OSC_D16),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+};
+
+static const struct mtk_parent dp_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_TVDPLL2_D4),
+	TOP_PARENT(CLK_TOP_TVDPLL2_D8),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D8),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D4),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D2),
+};
+
+static const struct mtk_parent dsp_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8),
+	TOP_PARENT(CLK_TOP_OSC_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+};
+
+static const struct mtk_parent ecc_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+};
+
+static const struct mtk_parent emi_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5),
+	APMIXED_PARENT(CLK_APMIXED_EMIPLL),
+};
+
+static const struct mtk_parent i2c_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_OSC_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D8),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2),
+};
+
+static const struct mtk_parent aud_engen1_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_APLL1_D4),
+};
+
+static const struct mtk_parent aud_engen2_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_APLL2_D4),
+};
+
+static const struct mtk_parent earc_engen_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_APLL1_D4),
+	TOP_PARENT(CLK_TOP_APLL2_D4),
+	TOP_PARENT(CLK_TOP_APLL3_D4),
+};
+
+static const struct mtk_parent spdifin_engen_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_APLL1_D4),
+	TOP_PARENT(CLK_TOP_APLL2_D4),
+	TOP_PARENT(CLK_TOP_APLL4_D4),
+};
+
+static const struct mtk_parent linein_engen_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_APLL1_D4),
+	TOP_PARENT(CLK_TOP_APLL2_D4),
+	TOP_PARENT(CLK_TOP_APLL5_D4),
+};
+
+static const struct mtk_parent audio_h_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2),
+	APMIXED_PARENT(CLK_APMIXED_APLL1),
+	APMIXED_PARENT(CLK_APMIXED_APLL2),
+};
+
+static const struct mtk_parent vadsp_vowpll_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	EXT_PARENT(CLK_PAD_CLK26M),
+};
+
+static const struct mtk_parent aud_1_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	APMIXED_PARENT(CLK_APMIXED_APLL1),
+};
+
+static const struct mtk_parent aud_2_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	APMIXED_PARENT(CLK_APMIXED_APLL2),
+};
+
+static const struct mtk_parent atb_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+};
+
+static const struct mtk_parent asm_h_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+};
+
+static const struct mtk_parent aud_i2s_m_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	APMIXED_PARENT(CLK_APMIXED_APLL1),
+	APMIXED_PARENT(CLK_APMIXED_APLL2),
+	APMIXED_PARENT(CLK_APMIXED_APLL3),
+	APMIXED_PARENT(CLK_APMIXED_APLL4),
+	APMIXED_PARENT(CLK_APMIXED_APLL5),
+};
+
+static const struct mtk_parent spdifin_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+};
+
+static const struct mtk_parent msdc50_0_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	APMIXED_PARENT(CLK_APMIXED_MSDCPLL),
+};
+
+static const struct mtk_parent axi_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_OSC_D4),
+};
+
+static const struct mtk_parent epd_dpi_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	EXT_PARENT(CLK_PAD_ANA_LVDS),
+	APMIXED_PARENT(CLK_APMIXED_TVDPLL1),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D2),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D4),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D8),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D16),
+};
+
+static const struct mtk_parent gcpu_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+};
+
+static const struct mtk_parent sflash_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D8),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+};
+
+static const struct mtk_parent spi_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+};
+
+static const struct mtk_parent vpll_dpix_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	EXT_PARENT(CLK_PAD_ANA_LVDS),
+	TOP_PARENT(CLK_TOP_MMPLL_D4_D4),
+	APMIXED_PARENT(CLK_APMIXED_TVDPLL1),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D2),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D4),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D8),
+	TOP_PARENT(CLK_TOP_TVDPLL1_D16),
+};
+
+static const struct mtk_parent disp_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D6_D2),
+	APMIXED_PARENT(CLK_APMIXED_TVDPLL2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D7),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+	TOP_PARENT(CLK_TOP_MMPLL_D5_D2),
+};
+
+static const struct mtk_parent nfi_b_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D8),
+	TOP_PARENT(CLK_TOP_MAINPLL_D7_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4),
+};
+
+static const struct mtk_parent epd_parents[] = {
+	EXT_PARENT(CLK_PAD_CLK26M),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D6_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2),
+	TOP_PARENT(CLK_TOP_MAINPLL_D6),
+	TOP_PARENT(CLK_TOP_MAINPLL_D5),
+	TOP_PARENT(CLK_TOP_MMPLL_D5),
+	APMIXED_PARENT(CLK_APMIXED_TVDPLL2),
+	TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+	TOP_PARENT(CLK_TOP_MMPLL_D5_D2),
+};
+
+#define MUX_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
+			_shift, _width, _upd_ofs, _upd) \
+	MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \
+			      _mux_clr_ofs, _shift, _width, -1, _upd_ofs, \
+			      _upd, CLK_MUX_SETCLR_UPD)
+
+#define MUX_GATE_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, \
+			     _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \
+			     _upd) \
+	MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \
+			      _mux_clr_ofs, _shift, _width, _gate, \
+			      _upd_ofs, _upd, CLK_MUX_SETCLR_UPD)
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_CFG_0 */
+	MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, axi_parents,
+			0x010, 0x014, 0x018, 0, 3, 0x04, 0),
+	MUX_CLR_SET_UPD(CLK_TOP_SPM_SEL, spm_parents,
+			0x010, 0x014, 0x018, 8, 2, 0x04, 1),
+	MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL, bus_aximem_parents,
+			0x010, 0x014, 0x018, 16, 3, 0x04, 2),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, disp_parents,
+			     0x010, 0x014, 0x018, 24, 4, 31, 0x04, 3),
+	/* CLK_CFG_1 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EPD_SEL, epd_parents,
+			     0x020, 0x024, 0x028, 0, 4, 7, 0x04, 4),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, mdp_parents,
+			     0x020, 0x024, 0x028, 8, 4, 15, 0x04, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, dp_parents,
+			     0x020, 0x024, 0x028, 16, 3, 23, 0x04, 6),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, img1_parents,
+			     0x020, 0x024, 0x028, 24, 4, 31, 0x04, 7),
+	/* CLK_CFG_2 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, ipe_parents,
+			     0x030, 0x034, 0x038, 0, 4, 7, 0x04, 8),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, cam_parents,
+			     0x030, 0x034, 0x038, 8, 4, 15, 0x04, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, camtm_parents,
+			     0x030, 0x034, 0x038, 16, 2, 23, 0x04, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, camtg_parents,
+			     0x030, 0x034, 0x038, 24, 4, 31, 0x04, 11),
+	/* CLK_CFG_3 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, camtg_parents,
+			     0x040, 0x044, 0x048, 0, 4, 7, 0x04, 12),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, mfg_ref_parents,
+			     0x040, 0x044, 0x048, 8, 2, 15, 0x04, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, uart_parents,
+			     0x040, 0x044, 0x048, 16, 1, 23, 0x04, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI0_SEL, spi_parents,
+			     0x040, 0x044, 0x048, 24, 3, 31, 0x04, 15),
+	/* CLK_CFG_4 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI1_SEL, spi_parents,
+			     0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI2_SEL, spi_parents,
+			     0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI3_SEL, spi_parents,
+			     0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI4_SEL, spi_parents,
+			     0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
+	/* CLK_CFG_5 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI5_SEL, spi_parents,
+			     0x060, 0x064, 0x068, 0, 3, 7, 0x04, 20),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2CP_SEL, i2cp_parents,
+			     0x060, 0x064, 0x068, 8, 3, 15, 0x04, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, i2c_parents,
+			     0x060, 0x064, 0x068, 16, 3, 23, 0x04, 22),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, seninf_parents,
+			     0x060, 0x064, 0x068, 24, 3, 31, 0x04, 23),
+	/* CLK_CFG_6 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, seninf_parents,
+			     0x070, 0x074, 0x078, 0, 3, 7, 0x04, 24),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, venc_parents,
+			     0x070, 0x074, 0x078, 8, 4, 15, 0x04, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, vdec_parents,
+			     0x070, 0x074, 0x078, 16, 4, 23, 0x04, 26),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, pwm_parents,
+			     0x070, 0x074, 0x078, 24, 2, 31, 0x04, 27),
+	/* CLK_CFG_7 */
+	MUX_CLR_SET_UPD(CLK_TOP_DVFSRC_SEL, oscd10_26m_parents,
+			0x080, 0x084, 0x088, 0, 1, 0x04, 28),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFBE_SEL, aes_msdcfbe_parents,
+			     0x080, 0x084, 0x088, 8, 3, 15, 0x04, 29),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, msdc_macro_parents,
+			     0x080, 0x084, 0x088, 16, 2, 23, 0x04, 30),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, msdc_macro_parents,
+			     0x080, 0x084, 0x088, 24, 2, 31, 0x08, 0),
+	/* CLK_CFG_8 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, msdc_macro_parents,
+			     0x090, 0x094, 0x098, 0, 2, 7, 0x08, 1),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
+			     0x090, 0x094, 0x098, 8, 3, 15, 0x08, 2),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, msdc30_parents,
+			     0x090, 0x094, 0x098, 16, 3, 23, 0x08, 3),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, msdc30_parents,
+			     0x090, 0x094, 0x098, 24, 3, 31, 0x08, 4),
+	/* CLK_CFG_9 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, msdc5hclk_parents,
+			     0x0a0, 0x0a4, 0x0a8, 0, 2, 7, 0x08, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, msdc30_1_h_parents,
+			     0x0a0, 0x0a4, 0x0a8, 8, 2, 15, 0x08, 6),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, msdc30_2_h_parents,
+			     0x0a0, 0x0a4, 0x0a8, 16, 2, 23, 0x08, 7),
+	MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, mcupm_parents,
+			0x0a0, 0x0a4, 0x0a8, 24, 2, 0x08, 8),
+	/* CLK_CFG_10 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, dsi_occ_parents,
+			     0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x08, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_KP_IRQ_GEN_SEL, kp_irq_gen_parents,
+			     0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x08, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI_BCLK_SEL, nfi_b_parents,
+			     0x0b0, 0x0b4, 0x0b8, 16, 4, 23, 0x08, 11),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, sflash_parents,
+			     0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x08, 12),
+	/* CLK_CFG_11 */
+	MUX_CLR_SET_UPD(CLK_TOP_EMI_SEL, emi_parents,
+			0x0c0, 0x0c4, 0x0c8, 0, 3, 0x08, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MAC_TL_SEL, pcie_mac_tl_parents,
+			     0x0c0, 0x0c4, 0x0c8, 8, 2, 15, 0x08, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M_SEL, snps_eth_250m_parents,
+			     0x0c0, 0x0c4, 0x0c8, 16, 1, 23, 0x08, 15),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP_SEL,
+			     snps_eth_62p4m_ptp_parents,
+			     0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x08, 16),
+	/* CLK_CFG_12 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII_SEL,
+			     snps_eth_50m_rmii_parents,
+			     0x0d0, 0x0d4, 0x0d8, 0, 1, 7, 0x08, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_LVDSTX_CLKDIG_CTS_SEL,
+			     lvdstx_clkdig_cts_parents,
+			     0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x08, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VPLL_DPIX_SEL, vpll_dpix_parents,
+			     0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x08, 19),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EPD_DPI_SEL, epd_dpi_parents,
+			     0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x08, 20),
+	/* CLK_CFG_13 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, dsp_parents,
+			     0x0e0, 0x0e4, 0x0e8, 0, 3, 7, 0x08, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, ecc_parents,
+			     0x0e0, 0x0e4, 0x0e8, 8, 3, 15, 0x08, 22),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, gcpu_parents,
+			     0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x08, 23),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P0_SEL, usb_parents,
+			     0x0e0, 0x0e4, 0x0e8, 24, 2, 31, 0x08, 24),
+	/* CLK_CFG_14 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P0_SEL, usb_parents,
+			     0x0f0, 0x0f4, 0x0f8, 0, 2, 7, 0x08, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P1_SEL, usb_parents,
+			     0x0f0, 0x0f4, 0x0f8, 8, 2, 15, 0x08, 26),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, usb_parents,
+			     0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x08, 27),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P2_SEL, usb_parents,
+			     0x0f0, 0x0f4, 0x0f8, 24, 2, 31, 0x08, 28),
+	/* CLK_CFG_15 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P2_SEL, usb_parents,
+			     0x100, 0x104, 0x108, 0, 2, 7, 0x08, 29),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,
+			     0x100, 0x104, 0x108, 8, 2, 15, 0x0c, 30),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents,
+			     0x100, 0x104, 0x108, 16, 1, 23, 0x0c, 0),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents,
+			     0x100, 0x104, 0x108, 24, 1, 31, 0x0c, 1),
+	/* CLK_CFG_16 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EARC_ENGEN_SEL, earc_engen_parents,
+			     0x110, 0x114, 0x118, 0, 2, 7, 0x0c, 2),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPDIFIN_ENGEN_SEL, spdifin_engen_parents,
+			     0x110, 0x114, 0x118, 8, 2, 15, 0x0c, 3),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_LINEIN_ENGEN_SEL, linein_engen_parents,
+			     0x110, 0x114, 0x118, 16, 2, 23, 0x0c, 4),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, audio_h_parents,
+			     0x110, 0x114, 0x118, 24, 2, 31, 0x0c, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VADSP_VOWPLL_SEL, vadsp_vowpll_parents,
+			     0x120, 0x124, 0x128, 0, 1, 7, 0x0c, 18),
+	MUX_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, pwrap_ulposc_parents,
+			0x120, 0x124, 0x128, 8, 2, 0x0c, 19),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, aud_1_parents,
+			     0x120, 0x124, 0x128, 16, 1, 23, 0x0c, 20),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, aud_2_parents,
+			     0x120, 0x124, 0x128, 24, 1, 31, 0x0c, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VADSP_26M_SEL, oscd10_26m_parents,
+			     0x130, 0x134, 0x138, 0, 1, 7, 0x0c, 22),
+	MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL, atb_parents,
+			0x130, 0x134, 0x138, 8, 2, 0x0c, 23),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H_SEL, asm_h_parents,
+			     0x240, 0x244, 0x248, 0, 2, 7, 0x0c, 24),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI4_M_SEL, aud_i2s_m_parents,
+			     0x240, 0x244, 0x248, 8, 3, 15, 0x0c, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI6_M_SEL, aud_i2s_m_parents,
+			     0x240, 0x244, 0x248, 16, 3, 23, 0x0c, 8),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO4_M_SEL, aud_i2s_m_parents,
+			     0x240, 0x244, 0x248, 24, 3, 31, 0x0c, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO5_M_SEL, aud_i2s_m_parents,
+			     0x250, 0x254, 0x258, 0, 3, 7, 0x0c, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO6_M_SEL, aud_i2s_m_parents,
+			     0x250, 0x254, 0x258, 8, 3, 15, 0x0c, 11),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_SEL, aud_i2s_m_parents,
+			     0x250, 0x254, 0x258, 16, 3, 23, 0x0c, 12),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPDIFIN_SEL, spdifin_parents,
+			     0x250, 0x254, 0x258, 24, 2, 31, 0x0c, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAN0_SEL, can0_parents,
+			     0x260, 0x264, 0x268, 0, 3, 7, 0x0c, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents,
+			     0x260, 0x264, 0x268, 8, 3, 15, 0x0c, 15),
+	MUX_CLR_SET_UPD(CLK_TOP_SSPM_SEL, sspm_parents,
+			0x260, 0x264, 0x268, 16, 3, 0x0c, 16),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VADSP_SEL, vadsp_parents,
+			     0x260, 0x264, 0x268, 24, 3, 31, 0x0c, 17),
+};
+
+static const struct mtk_gate_regs top_cg_regs = {
+	.set_ofs = 0x508,
+	.clr_ofs = 0x50C,
+	.sta_ofs = 0x504,
+};
+
+#define GATE_EXT(_id, _parent, _shift)  \
+	GATE_FLAGS(_id, _parent, &top_cg_regs, _shift,\
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR_INV)
+
+#define GATE_TOP(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &top_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR_INV)
+
+static const struct mtk_gate top_gates[] = {
+	/* TOP1 */
+	GATE_EXT(CLK_TOP_F26M_CK_EN, CLK_PAD_CLK26M, 2),
+	GATE_EXT(CLK_TOP_USB_F26M_CK_EN, CLK_PAD_CLK26M, 3),
+	GATE_EXT(CLK_TOP_USB2_PHY_REFCK_P0_EN, CLK_PAD_CLK26M, 4),
+	GATE_EXT(CLK_TOP_USB2_PHY_REFCK_P1_EN, CLK_PAD_CLK26M, 5),
+	GATE_EXT(CLK_TOP_USB2_PHY_REFCK_P2_EN, CLK_PAD_CLK26M, 6),
+	GATE_EXT(CLK_TOP_USB2_26M_CK_P0_EN, CLK_PAD_CLK26M, 7),
+	GATE_EXT(CLK_TOP_USB2_26M_CK_P1_EN, CLK_PAD_CLK26M, 8),
+	GATE_EXT(CLK_TOP_USB2_26M_CK_P2_EN, CLK_PAD_CLK26M, 9),
+	GATE_TOP(CLK_TOP_FMCNT_P0_EN, CLK_TOP_UNIVPLL_192M_D4, 10),
+	GATE_TOP(CLK_TOP_FMCNT_P1_EN, CLK_TOP_UNIVPLL_192M_D4, 11),
+	GATE_TOP(CLK_TOP_FMCNT_P2_EN, CLK_TOP_UNIVPLL_192M_D4, 12),
+};
+
+static const struct mtk_clk_tree mt8366_topckgen_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.fdivs_offs = CLK_TOP_MAINPLL_D4,
+	.muxes_offs = CLK_TOP_AXI_SEL,
+	.gates_offs = CLK_TOP_F26M_CK_EN,
+	.fdivs = top_divs,
+	.muxes = top_muxes,
+	.gates = top_gates,
+	.num_fdivs = ARRAY_SIZE(top_divs),
+	.num_muxes = ARRAY_SIZE(top_muxes),
+	.num_gates = ARRAY_SIZE(top_gates),
+	.type = MTK_CLK_TREE_TOPCKGEN,
+};
+
+/* infracfg */
+
+static const struct mtk_gate_regs infracfg_ao_reg0_cg_regs = {
+	.set_ofs = 0x10,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs infracfg_ao_reg1_cg_regs = {
+	.set_ofs = 0x1c,
+	.clr_ofs = 0x20,
+	.sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs infracfg_ao_reg2_cg_regs = {
+	.set_ofs = 0x80,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infracfg_ao_reg3_cg_regs = {
+	.set_ofs = 0x88,
+	.clr_ofs = 0x8c,
+	.sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infracfg_ao_reg4_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xa8,
+	.sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infracfg_ao_reg5_cg_regs = {
+	.set_ofs = 0xc0,
+	.clr_ofs = 0xc4,
+	.sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infracfg_ao_reg6_cg_regs = {
+	.set_ofs = 0xf0,
+	.clr_ofs = 0xf4,
+	.sta_ofs = 0xf8,
+};
+
+#define GATE_INFRACFG_AO_REG0(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg0_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG0E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg0_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG1(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg1_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG1E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg1_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG2(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg2_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG2E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg2_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG3(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg3_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG3E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg3_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG4(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg4_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG4E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg4_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG5(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg5_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG5E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg5_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG6(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg6_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_INFRACFG_AO_REG6E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &infracfg_ao_reg6_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_SETCLR)
+
+static const struct mtk_gate infracfg_ao_reg_clks[] = {
+	/* INFRACFG_AO_REG0 */
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_UART0, CLK_TOP_AXI_SEL, 0),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_UART1, CLK_TOP_AXI_SEL, 1),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_UART2, CLK_TOP_AXI_SEL, 2),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_UART3, CLK_TOP_AXI_SEL, 3),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_DISP_PWM0, CLK_TOP_DISP_PWM_SEL, 10),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_DISP_PWM1, CLK_TOP_DISP_PWM_SEL, 11),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI0_B, CLK_TOP_SPI0_SEL, 12),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI1_B, CLK_TOP_SPI1_SEL, 13),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI2_B, CLK_TOP_SPI2_SEL, 14),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI3_B, CLK_TOP_SPI3_SEL, 15),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI4_B, CLK_TOP_SPI4_SEL, 16),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI5_B, CLK_TOP_SPI5_SEL, 17),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI0_H, CLK_TOP_AXI_SEL, 18),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI1_H, CLK_TOP_AXI_SEL, 19),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI2_H, CLK_TOP_AXI_SEL, 20),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI3_H, CLK_TOP_AXI_SEL, 21),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI4_H, CLK_TOP_AXI_SEL, 22),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_SPI5_H, CLK_TOP_AXI_SEL, 23),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_AXI, CLK_TOP_EMI_SEL, 24),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_AHB, CLK_TOP_AXI_SEL, 25),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_TL, CLK_TOP_MAC_TL_SEL, 26),
+	GATE_INFRACFG_AO_REG0E(CLK_INFRACFG_AO_REGP_REF, CLK_PAD_CLK26M, 27),
+	GATE_INFRACFG_AO_REG0(CLK_INFRACFG_AO_REGP_DMA_B, CLK_TOP_AXI_SEL, 30),
+	/* INFRACFG_AO_REG1 */
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB0_PIPE, CLK_PAD_CLK26M, 0),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB0_REF, CLK_PAD_CLK26M, 1),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB0_FRMCNT, CLK_PAD_CLK26M, 2),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB0_UTMI, CLK_PAD_CLK26M, 3),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB0_SYS, CLK_TOP_USB_TOP_P0_SEL, 4),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB0_XCHI, CLK_TOP_USB_XHCI_P0_SEL, 5),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB0_F, CLK_TOP_AXI_SEL, 6),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB0_H, CLK_TOP_AXI_SEL, 7),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB1_REF, CLK_PAD_CLK26M, 8),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB1_FRMCNT, CLK_PAD_CLK26M, 9),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB1_UTMI, CLK_PAD_CLK26M, 10),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB1_SYS, CLK_TOP_USB_TOP_P1_SEL, 11),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB1_XCHI, CLK_TOP_USB_XHCI_P1_SEL, 12),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB1_F, CLK_TOP_AXI_SEL, 13),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB1_H, CLK_TOP_AXI_SEL, 14),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB2_REF, CLK_PAD_CLK26M, 15),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB2_FRMCNT, CLK_PAD_CLK26M, 16),
+	GATE_INFRACFG_AO_REG1E(CLK_INFRACFG_AO_REGP_SSUSB2_UTMI, CLK_PAD_CLK26M, 17),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB2_SYS, CLK_TOP_USB_TOP_P2_SEL, 18),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB2_XCHI, CLK_TOP_USB_XHCI_P2_SEL, 19),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB2_F, CLK_TOP_AXI_SEL, 20),
+	GATE_INFRACFG_AO_REG1(CLK_INFRACFG_AO_REGP_SSUSB2_H, CLK_TOP_AXI_SEL, 21),
+	/* INFRACFG_AO_REG2 */
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PMIC_TMR, CLK_TOP_PWRAP_ULPOSC_SEL, 0),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PMIC_AP, CLK_TOP_PWRAP_ULPOSC_SEL, 1),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_SEJ, CLK_TOP_AXI_SEL, 5),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_MCUPM, CLK_TOP_MCUPM_SEL, 7),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_GCE, CLK_TOP_AXI_SEL, 8),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_GCE2, CLK_TOP_AXI_SEL, 9),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PWM_H, CLK_TOP_AXI_SEL, 15),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PWM1, CLK_TOP_PWM_SEL, 16),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PWM2, CLK_TOP_PWM_SEL, 17),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PWM3, CLK_TOP_PWM_SEL, 18),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PWM4, CLK_TOP_PWM_SEL, 19),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_PWM, CLK_TOP_PWM_SEL, 21),
+	GATE_INFRACFG_AO_REG2E(CLK_INFRACFG_AO_REG_GCE_26M, CLK_PAD_CLK26M, 27),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28),
+	GATE_INFRACFG_AO_REG2(CLK_INFRACFG_AO_REG_BTIF, CLK_TOP_AXI_SEL, 31),
+	/* INFRACFG_AO_REG3 */
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_SPI0, CLK_TOP_SPI0_SEL, 1),
+	GATE_INFRACFG_AO_REG3E(CLK_INFRACFG_AO_REG_AUXADC, CLK_PAD_CLK26M, 10),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_CPUM, CLK_TOP_AXI_SEL, 11),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_CCIF1_AP, CLK_TOP_AXI_SEL, 12),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_CCIF1_MD, CLK_TOP_AXI_SEL, 13),
+	GATE_INFRACFG_AO_REG3E(CLK_INFRACFG_AO_REG_AUXADC_MD, CLK_PAD_CLK26M, 14),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_TL_26M, CLK_TOP_AXI_SEL, 15),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_TL_96M, CLK_TOP_AXI_SEL, 18),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_PL_P_250M, CLK_TOP_AXI_SEL, 19),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_CCIF_AP, CLK_TOP_AXI_SEL, 23),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_AUDIO, CLK_TOP_AXI_SEL, 25),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_CCIF_MD, CLK_TOP_AXI_SEL, 26),
+	GATE_INFRACFG_AO_REG3(CLK_INFRACFG_AO_REG_DBG_TRACE, CLK_TOP_AXI_SEL, 29),
+	/* INFRACFG_AO_REG4 */
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_CLDMA_BCLK, CLK_TOP_AXI_SEL, 3),
+	GATE_INFRACFG_AO_REG4E(CLK_INFRACFG_AO_REG_AUDIO_26M_BCLK, CLK_PAD_CLK26M, 4),
+	GATE_INFRACFG_AO_REG4E(CLK_INFRACFG_AO_REG_MODEM_TEMP_SHARE, CLK_PAD_CLK26M, 5),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_SPI1, CLK_TOP_SPI1_SEL, 6),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_SPI2, CLK_TOP_SPI2_SEL, 9),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_SPI3, CLK_TOP_SPI3_SEL, 10),
+	GATE_INFRACFG_AO_REG4E(CLK_INFRACFG_AO_REG_U_SAP_B, CLK_PAD_CLK26M, 13),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_UNIPRO_MBIST, CLK_TOP_AXI_SEL, 16),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_SPI4, CLK_TOP_SPI4_SEL, 25),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_SPI5, CLK_TOP_SPI5_SEL, 26),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_CQ_DMA, CLK_TOP_AXI_SEL, 27),
+	GATE_INFRACFG_AO_REG4(CLK_INFRACFG_AO_REG_KP_IRQ_GEN, CLK_TOP_KP_IRQ_GEN_SEL, 28),
+	GATE_INFRACFG_AO_REG4E(CLK_INFRACFG_AO_REG_KP_32K, CLK_PAD_CLK32K, 29),
+	/* INFRACFG_AO_REG5 */
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_U_AXI, CLK_TOP_AXI_SEL, 5),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF5_AP, CLK_TOP_AXI_SEL, 9),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF5_MD, CLK_TOP_AXI_SEL, 10),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF2_AP, CLK_TOP_AXI_SEL, 16),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF2_MD, CLK_TOP_AXI_SEL, 17),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF3_AP, CLK_TOP_AXI_SEL, 18),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF3_MD, CLK_TOP_AXI_SEL, 19),
+	GATE_INFRACFG_AO_REG5E(CLK_INFRACFG_AO_REG_SEJ_F13M, CLK_PAD_CLK26M, 20),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_AES, CLK_TOP_AXI_SEL, 21),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_GCPU, CLK_TOP_GCPU_SEL, 26),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_ECC, CLK_TOP_ECC_SEL, 27),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF4_AP, CLK_TOP_AXI_SEL, 28),
+	GATE_INFRACFG_AO_REG5(CLK_INFRACFG_AO_REG_CCIF4_MD, CLK_TOP_AXI_SEL, 29),
+	/* INFRACFG_AO_REG6 */
+	GATE_INFRACFG_AO_REG6E(CLK_INFRACFG_AO_REGP_AUXADC_26M, CLK_PAD_CLK26M, 0),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC0, CLK_TOP_MSDC50_0_SEL, 1),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC0_H, CLK_TOP_MSDC50_0_HCLK_SEL, 2),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC0_FAES, CLK_TOP_AES_MSDCFBE_SEL, 3),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC0_MST_F, CLK_TOP_AXI_SEL, 4),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC0_SLV_H, CLK_TOP_AXI_SEL, 5),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC1, CLK_TOP_MSDC30_1_SEL, 6),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC1_H, CLK_TOP_MSDC30_1_HCLK_SEL, 7),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC1_MST_F, CLK_TOP_AXI_SEL, 8),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC1_SLV_H, CLK_TOP_AXI_SEL, 9),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC2, CLK_TOP_MSDC30_2_SEL, 10),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC2_H, CLK_TOP_MSDC30_2_HCLK_SEL, 11),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC2_MST_F, CLK_TOP_AXI_SEL, 12),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_MSDC2_SLV_H, CLK_TOP_AXI_SEL, 13),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_SFLASH, CLK_TOP_SFLASH_SEL, 14),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_SFLASH_F, CLK_TOP_AXI_SEL, 15),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_SFLASH_H, CLK_TOP_AXI_SEL, 16),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_SFLASH_P, CLK_TOP_AXI_SEL, 17),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_BTIF_B, CLK_TOP_AXI_SEL, 18),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_CAN0_P, CLK_TOP_AXI_SEL, 20),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_CAN0, CLK_TOP_CAN0_SEL, 21),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_NFI_H, CLK_TOP_AXI_SEL, 22),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_NFI_B, CLK_TOP_NFI_BCLK_SEL, 23),
+	GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_NFIECC_B, CLK_TOP_NFI_BCLK_SEL, 24),
+};
+
+static const struct mtk_clk_tree infracfg_ao_reg_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = infracfg_ao_reg_clks,
+	.num_gates = ARRAY_SIZE(infracfg_ao_reg_clks),
+};
+
+static const struct mtk_gate_regs impc_cg_regs = {
+	.set_ofs = 0xe08,
+	.clr_ofs = 0xe04,
+	.sta_ofs = 0xe00,
+};
+
+#define GATE_IMPC(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &impc_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate impc_clks[] = {
+	GATE_IMPC(CLK_IMPC_I2C1, CLK_TOP_I2CP_SEL, 0),
+	GATE_IMPC(CLK_IMPC_I2C2, CLK_TOP_I2CP_SEL, 1),
+	GATE_IMPC(CLK_IMPC_I2C3, CLK_TOP_I2CP_SEL, 2),
+	GATE_IMPC(CLK_IMPC_I2C5, CLK_TOP_I2CP_SEL, 3),
+	GATE_IMPC(CLK_IMPC_I2C6, CLK_TOP_I2CP_SEL, 4),
+	GATE_IMPC(CLK_IMPC_I2C7, CLK_TOP_I2CP_SEL, 5),
+	GATE_IMPC(CLK_IMPC_I2C8, CLK_TOP_I2CP_SEL, 6),
+	GATE_IMPC(CLK_IMPC_I2C9, CLK_TOP_I2CP_SEL, 7),
+};
+
+static const struct mtk_clk_tree impc_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = impc_clks,
+	.num_gates = ARRAY_SIZE(impc_clks),
+};
+
+static const struct mtk_gate_regs impe_cg_regs = {
+	.set_ofs = 0xe08,
+	.clr_ofs = 0xe04,
+	.sta_ofs = 0xe00,
+};
+
+#define GATE_IMPE(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &impe_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate impe_clks[] = {
+	GATE_IMPE(CLK_IMPE_I2C0, CLK_TOP_I2C_SEL, 0),
+	GATE_IMPE(CLK_IMPE_I2C4, CLK_TOP_I2C_SEL, 1),
+};
+
+static const struct mtk_clk_tree impe_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = impe_clks,
+	.num_gates = ARRAY_SIZE(impe_clks),
+};
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+	.set_ofs = 0x100,
+	.clr_ofs = 0x100,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+	.set_ofs = 0x110,
+	.clr_ofs = 0x110,
+	.sta_ofs = 0x110,
+};
+
+#define GATE_MM0(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &mm0_cg_regs, _shift,	\
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_NO_SETCLR)
+
+#define GATE_MM1(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &mm1_cg_regs, _shift,	\
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_NO_SETCLR)
+
+#define GATE_MM1E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &mm1_cg_regs, _shift,	\
+		   CLK_PARENT_EXT | CLK_GATE_NO_SETCLR)
+
+static const struct mtk_gate mm_clks[] = {
+	/* MM0 */
+	GATE_MM0(CLK_MM_DISP_OVL0_4L, CLK_TOP_DISP_SEL, 0),
+	GATE_MM0(CLK_MM_DISP_OVL1_4L, CLK_TOP_DISP_SEL, 1),
+	GATE_MM0(CLK_MM_DISP_RSZ0, CLK_TOP_DISP_SEL, 2),
+	GATE_MM0(CLK_MM_DISP_RSZ1, CLK_TOP_DISP_SEL, 3),
+	GATE_MM0(CLK_MM_DISP_RDMA0, CLK_TOP_DISP_SEL, 4),
+	GATE_MM0(CLK_MM_DISP_RDMA1, CLK_TOP_DISP_SEL, 5),
+	GATE_MM0(CLK_MM_DISP_COLOR1, CLK_TOP_DISP_SEL, 7),
+	GATE_MM0(CLK_MM_DISP_CCORR1, CLK_TOP_DISP_SEL, 9),
+	GATE_MM0(CLK_MM_DISP_CCORR3, CLK_TOP_DISP_SEL, 11),
+	GATE_MM0(CLK_MM_DISP_AAL1, CLK_TOP_DISP_SEL, 13),
+	GATE_MM0(CLK_MM_DISP_GAMMA1, CLK_TOP_DISP_SEL, 15),
+	GATE_MM0(CLK_MM_DISP_DITHER1, CLK_TOP_DISP_SEL, 17),
+	GATE_MM0(CLK_MM_VPP_MERGE0, CLK_TOP_DISP_SEL, 19),
+	GATE_MM0(CLK_MM_DISP_DSI0_MM, CLK_TOP_DISP_SEL, 21),
+	GATE_MM0(CLK_MM_DP_INTF0_MM, CLK_TOP_DISP_SEL, 22),
+	GATE_MM0(CLK_MM_DPI0_MM, CLK_TOP_DISP_SEL, 23),
+	GATE_MM0(CLK_MM_DISP_WDMA0, CLK_TOP_DISP_SEL, 24),
+	GATE_MM0(CLK_MM_DISP_DSI1_MM, CLK_TOP_DISP_SEL, 25),
+	GATE_MM0(CLK_MM_DISP_FAKE_ENG0, CLK_TOP_DISP_SEL, 26),
+	GATE_MM0(CLK_MM_DISP_FAKE_ENG1, CLK_TOP_DISP_SEL, 27),
+	GATE_MM0(CLK_MM_SMI_SUB_COMMON, CLK_TOP_DISP_SEL, 28),
+	GATE_MM0(CLK_MM_DISP_MUTEX0, CLK_TOP_DISP_SEL, 29),
+	GATE_MM0(CLK_MM_DISP_APB_BUS, CLK_TOP_DISP_SEL, 30),
+	GATE_MM0(CLK_MM_LVDS_ENCODER, CLK_TOP_DISP_SEL, 31),
+	/* MM1 */
+	GATE_MM1(CLK_MM_EPD_DLI_ASYNC, CLK_TOP_DISP_SEL, 0),
+	GATE_MM1(CLK_MM_SMI, CLK_TOP_DISP_SEL, 1),
+	GATE_MM1(CLK_MM_DISP_DSI0, CLK_TOP_DSI_OCC_SEL, 2),
+	GATE_MM1(CLK_MM_DPI0, CLK_TOP_VPLL_DPIX_SEL, 3),
+	GATE_MM1(CLK_MM_LVDS_ENCODER_PXL, CLK_TOP_VPLL_DPIX_SEL, 4),
+	GATE_MM1(CLK_MM_DISP_DSI1, CLK_TOP_DSI_OCC_SEL, 5),
+	GATE_MM1(CLK_MM_DP_INTF0, CLK_TOP_DP_SEL, 6),
+	GATE_MM1(CLK_MM_LVDS_ENCODER_CTS, CLK_TOP_LVDSTX_CLKDIG_CTS_SEL, 7),
+	GATE_MM1(CLK_MM_AXI, CLK_TOP_AXI_SEL, 8),
+	GATE_MM1(CLK_MM_EPDSYS, CLK_TOP_EPD_SEL, 9),
+	GATE_MM1(CLK_MM_MM_CK_GLOBAL, CLK_TOP_DISP_SEL, 10),
+	GATE_MM1(CLK_MM_DISP_DSI0_CK_GLOBAL, CLK_TOP_DSI_OCC_SEL, 11),
+	GATE_MM1(CLK_MM_LVDS_PXL_CK_GLOBAL, CLK_TOP_VPLL_DPIX_SEL, 12),
+	GATE_MM1(CLK_MM_DISP_DSI1_GLOBAL, CLK_TOP_DSI_OCC_SEL, 13),
+	GATE_MM1(CLK_MM_DP_CK_GLOBAL, CLK_TOP_DP_SEL, 14),
+	GATE_MM1(CLK_MM_LVDS_CTS_CK_GLOBAL, CLK_TOP_LVDSTX_CLKDIG_CTS_SEL, 15),
+	GATE_MM1(CLK_MM_AXI_CK_GLOBAL, CLK_TOP_AXI_SEL, 16),
+	GATE_MM1(CLK_MM_EPDSYS_CK_GLOBAL, CLK_TOP_EPD_SEL, 17),
+	GATE_MM1E(CLK_MM_26M, CLK_PAD_CLK26M, 18),
+	GATE_MM1E(CLK_MM_32K, CLK_PAD_CLK32K, 19),
+};
+
+static const struct mtk_clk_tree mm_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = mm_clks,
+	.num_gates = ARRAY_SIZE(mm_clks),
+};
+
+static const struct mtk_gate_regs dptx_phyd_sifslv_dig_glb_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x8,
+};
+
+#define GATE_DPTX_PHYD_SIFSLV_DIG_GLB(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &dptx_phyd_sifslv_dig_glb_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_NO_SETCLR_INV)
+
+static const struct mtk_gate dptx_phyd_sifslv_dig_glb_clks[] = {
+	GATE_DPTX_PHYD_SIFSLV_DIG_GLB(CLK_DPTX_PHYD_SIFSLV_DIG_GLB_RG_REF_CK_ENA,
+				      CLK_PAD_CLK26M, 0),
+};
+
+static const struct mtk_clk_tree dptx_phyd_sifslv_dig_glb_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = dptx_phyd_sifslv_dig_glb_clks,
+	.num_gates = ARRAY_SIZE(dptx_phyd_sifslv_dig_glb_clks),
+};
+
+static const struct mtk_gate_regs epdsys_config0_cg_regs = {
+	.set_ofs = 0x100,
+	.clr_ofs = 0x100,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs epdsys_config1_cg_regs = {
+	.set_ofs = 0x110,
+	.clr_ofs = 0x110,
+	.sta_ofs = 0x110,
+};
+
+#define GATE_EPDSYS_CONFIG0(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &epdsys_config0_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_NO_SETCLR)
+
+#define GATE_EPDSYS_CONFIG1(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &epdsys_config1_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_NO_SETCLR)
+
+#define GATE_EPDSYS_CONFIG1E(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &epdsys_config1_cg_regs, _shift, \
+		   CLK_PARENT_EXT | CLK_GATE_NO_SETCLR)
+
+static const struct mtk_gate epdsys_config_clks[] = {
+	/* EPDSYS_CONFIG0 */
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_TOP, CLK_TOP_EPD_SEL, 0),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_IMAGE_RDMA, CLK_TOP_EPD_SEL, 1),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_WORKING_RDMA, CLK_TOP_EPD_SEL, 2),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_WDMA, CLK_TOP_EPD_SEL, 3),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_WF_LUT_TOP, CLK_TOP_EPD_SEL, 4),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_DPI, CLK_TOP_EPD_SEL, 5),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_6, CLK_TOP_EPD_SEL, 6),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_PIPELINE_IMAGE_PROCESS, CLK_TOP_EPD_SEL, 7),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_DISP_COLOR, CLK_TOP_EPD_SEL, 12),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_DISP_CCORR, CLK_TOP_EPD_SEL, 13),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_DPI, CLK_TOP_EPD_DPI_SEL, 19),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_TCON, CLK_TOP_EPD_DPI_SEL, 20),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_SMI_LARB3, CLK_TOP_EPD_SEL, 23),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_SMI_LARB8, CLK_TOP_EPD_SEL, 26),
+	GATE_EPDSYS_CONFIG0(CLK_EPDSYS_IMG_DL_RELAY, CLK_TOP_EPD_SEL, 29),
+	/* EPDSYS_CONFIG1 */
+	GATE_EPDSYS_CONFIG1E(CLK_EPDSYS_26M_HRTWT, CLK_PAD_CLK26M, 0),
+	GATE_EPDSYS_CONFIG1(CLK_EPDSYS_DPI0_MM, CLK_TOP_EPD_SEL, 1),
+};
+
+static const struct mtk_clk_tree epdsys_config_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = epdsys_config_clks,
+	.num_gates = ARRAY_SIZE(epdsys_config_clks),
+};
+
+static const struct mtk_gate_regs vde23_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0xc,
+	.sta_ofs = 0x8,
+};
+
+#define GATE_VDE23(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vde23_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR_INV)
+
+static const struct mtk_gate vdec_gcon_clks[] = {
+	GATE_VDE23(CLK_VDE2_LARB1_CKEN, CLK_TOP_VDEC_SEL, 0),
+};
+
+static const struct mtk_clk_tree vdec_gcon_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = vdec_gcon_clks,
+	.num_gates = ARRAY_SIZE(vdec_gcon_clks),
+};
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_IPE(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &ipe_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate ipesys_clks[] = {
+	GATE_IPE(CLK_IPE_LARB19, CLK_TOP_IPE_SEL, 0),
+	GATE_IPE(CLK_IPE_LARB20, CLK_TOP_IPE_SEL, 1),
+	GATE_IPE(CLK_IPE_SMI_SUBCOM, CLK_TOP_IPE_SEL, 2),
+	GATE_IPE(CLK_IPE_FD, CLK_TOP_IPE_SEL, 3),
+	GATE_IPE(CLK_IPE_FE, CLK_TOP_IPE_SEL, 4),
+	GATE_IPE(CLK_IPE_RSC, CLK_TOP_IPE_SEL, 5),
+	GATE_IPE(CLK_IPE_GALS, CLK_TOP_IPE_SEL, 8),
+};
+
+static const struct mtk_clk_tree ipesys_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ipesys_clks,
+	.num_gates = ARRAY_SIZE(ipesys_clks),
+};
+
+static const struct mtk_gate_regs cam_m_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_CAM_M(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &cam_m_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate camsys_main_clks[] = {
+	GATE_CAM_M(CLK_CAM_M_LARB13, CLK_TOP_CAM_SEL, 0),
+	GATE_CAM_M(CLK_CAM_M_DFP_VAD, CLK_TOP_CAM_SEL, 1),
+	GATE_CAM_M(CLK_CAM_M_LARB14, CLK_TOP_CAM_SEL, 2),
+	GATE_CAM_M(CLK_CAM_M_CAM, CLK_TOP_CAM_SEL, 6),
+	GATE_CAM_M(CLK_CAM_M_CAMTG, CLK_TOP_CAM_SEL, 7),
+	GATE_CAM_M(CLK_CAM_M_SENINF, CLK_TOP_CAM_SEL, 8),
+	GATE_CAM_M(CLK_CAM_M_CAMSV1, CLK_TOP_CAM_SEL, 10),
+	GATE_CAM_M(CLK_CAM_M_CAMSV2, CLK_TOP_CAM_SEL, 11),
+	GATE_CAM_M(CLK_CAM_M_CAMSV3, CLK_TOP_CAM_SEL, 12),
+	GATE_CAM_M(CLK_CAM_M_CCU0, CLK_TOP_CAM_SEL, 13),
+	GATE_CAM_M(CLK_CAM_M_CCU1, CLK_TOP_CAM_SEL, 14),
+	GATE_CAM_M(CLK_CAM_M_MRAW0, CLK_TOP_CAM_SEL, 15),
+	GATE_CAM_M(CLK_CAM_M_FAKE_ENG, CLK_TOP_CAM_SEL, 17),
+	GATE_CAM_M(CLK_CAM_M_CCU_GALS, CLK_TOP_CAM_SEL, 18),
+	GATE_CAM_M(CLK_CAM_M_CAM2MM_GALS, CLK_TOP_CAM_SEL, 19),
+	GATE_CAM_M(CLK_CAM_M_CAMSV4, CLK_TOP_CAM_SEL, 20),
+	GATE_CAM_M(CLK_CAM_M_PDA, CLK_TOP_CAM_SEL, 21),
+};
+
+static const struct mtk_clk_tree camsys_main_clks_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = camsys_main_clks,
+	.num_gates = ARRAY_SIZE(camsys_main_clks),
+};
+
+static const struct udevice_id mt8366_apmixed_compat[] = {
+	{
+		.compatible = "mediatek,mt8366-apmixedsys",
+		.data = (ulong)&mt8366_apmixed_tree,
+	},
+	{ }
+};
+
+static const struct udevice_id mt8366_clk_compat[] = {
+	{
+		.compatible = "mediatek,mt8366-topckgen",
+		.data = (ulong)&mt8366_topckgen_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-infracfg-ao",
+		.data = (ulong)&infracfg_ao_reg_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-iic-wrap-c",
+		.data = (ulong)&impc_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-iic-wrap-e",
+		.data = (ulong)&impe_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-mmsys",
+		.data = (ulong)&mm_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-dptx",
+		.data = (ulong)&dptx_phyd_sifslv_dig_glb_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-epdsys",
+		.data = (ulong)&epdsys_config_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-vdec-gcon",
+		.data = (ulong)&vdec_gcon_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-ipesys",
+		.data = (ulong)&ipesys_clks_tree,
+	},
+	{
+		.compatible = "mediatek,mt8366-camsys-main",
+		.data = (ulong)&camsys_main_clks_tree,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(mt8366_clk_apmixedsys) = {
+	.name = "mt8366-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt8366_apmixed_compat,
+	.probe = mtk_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mt8366_clk) = {
+	.name = "mt8366-clk",
+	.id = UCLASS_CLK,
+	.of_match = mt8366_clk_compat,
+	.probe = mtk_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 13c248c93a6..70cc7624a14 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -35,8 +35,6 @@
 #define SCP_AXICK_DCM_DIS_EN		BIT(0)
 #define SCP_AXICK_26M_SEL_EN		BIT(4)
 
-static struct udevice *mtk_clk_providers[MTK_CLK_TREE_NUM_TYPES];
-
 static bool mtk_clk_tree_type_is_provider(enum mtk_clk_tree_type type)
 {
 	return type != MTK_CLK_TREE_NONE && type < MTK_CLK_TREE_NUM_TYPES;
@@ -58,44 +56,40 @@ static enum mtk_clk_tree_type mtk_clk_tree_type_from_parent_flags(u16 flags)
 
 static struct udevice *mtk_clk_tree_get_provider(enum mtk_clk_tree_type type)
 {
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
 	if (!mtk_clk_tree_type_is_provider(type))
 		return NULL;
 
-	if (!mtk_clk_providers[type]) {
-		struct udevice *dev;
-		struct uclass *uc;
-		int ret;
-
-		/* Lazily probe and register the requested provider. */
-		ret = uclass_get(UCLASS_CLK, &uc);
-		if (ret)
-			return ERR_PTR(ret);
+	ret = uclass_get(UCLASS_CLK, &uc);
+	if (ret)
+		return ERR_PTR(ret);
 
-		uclass_foreach_dev(dev, uc) {
-			const struct mtk_clk_tree *tree;
-			const void *ops;
+	uclass_foreach_dev(dev, uc) {
+		const struct mtk_clk_tree *tree;
+		const void *ops;
 
-			ops = dev_get_driver_ops(dev);
-			if (ops != &mtk_clk_apmixedsys_ops &&
-			    ops != &mtk_clk_fixed_pll_ops &&
-			    ops != &mtk_clk_topckgen_ops &&
-			    ops != &mtk_clk_infrasys_ops)
-				continue;
+		ops = dev_get_driver_ops(dev);
+		if (ops != &mtk_clk_apmixedsys_ops &&
+		    ops != &mtk_clk_fixed_pll_ops &&
+		    ops != &mtk_clk_topckgen_ops &&
+		    ops != &mtk_clk_infrasys_ops)
+			continue;
 
-			tree = (const void *)dev_get_driver_data(dev);
-			if (tree->type != type)
-				continue;
+		tree = (const void *)dev_get_driver_data(dev);
+		if (tree->type != type)
+			continue;
 
-			/* Probe will add it to mtk_clk_providers[type]. */
-			ret = device_probe(dev);
-			if (ret)
-				return ERR_PTR(ret);
+		ret = device_probe(dev);
+		if (ret)
+			return ERR_PTR(ret);
 
-			break;
-		}
+		return dev;
 	}
 
-	return mtk_clk_providers[type] ?: ERR_PTR(-ENOENT);
+	return ERR_PTR(-ENOENT);
 }
 
 static struct udevice *mtk_clk_parent_get_provider(u16 flags)
@@ -103,20 +97,6 @@ static struct udevice *mtk_clk_parent_get_provider(u16 flags)
 	return mtk_clk_tree_get_provider(mtk_clk_tree_type_from_parent_flags(flags));
 }
 
-static int mtk_clk_tree_register_provider(struct udevice *dev,
-					  const struct mtk_clk_tree *tree)
-{
-	if (!mtk_clk_tree_type_is_provider(tree->type))
-		return 0;
-
-	if (mtk_clk_providers[tree->type])
-		return -EEXIST;
-
-	mtk_clk_providers[tree->type] = dev;
-
-	return 0;
-}
-
 /* shared functions */
 
 static const int mtk_common_clk_of_xlate(struct clk *clk,
@@ -1128,5 +1108,5 @@ int mtk_clk_probe(struct udevice *dev)
 
 	priv->tree = tree;
 
-	return mtk_clk_tree_register_provider(dev, tree);
+	return 0;
 }
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 12b0e2c9914..bd8b1f8cf5b 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -113,6 +113,16 @@ config MT8188_POWER_DOMAIN
 	  the SoC power domains on and off and handles the associated bus
 	  protection steps, per-domain clocks and parent domains.
 
+config MT8366_POWER_DOMAIN
+	bool "Enable the MediaTek power domain driver for MT8366 compatible SoC"
+	depends on POWER_DOMAIN && ARCH_MEDIATEK
+	select MTK_POWER_DOMAIN
+	help
+	  Enable support for manipulating MediaTek power domains via MMIO
+	  mapped registers for MT8366 compatible SoC. The driver powers
+	  the SoC power domains on and off and handles the associated bus
+	  protection steps, per-domain clocks and parent domains.
+
 config MTK_POWER_DOMAIN
 	bool
 	depends on POWER_DOMAIN && ARCH_MEDIATEK
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index e6fe71c374a..74f22d57981 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o
 obj-$(CONFIG_MT2701_POWER_DOMAIN) += mt2701-power-domain.o
 obj-$(CONFIG_MT7622_POWER_DOMAIN) += mt7622-power-domain.o
 obj-$(CONFIG_MT8188_POWER_DOMAIN) += mt8188-power-domain.o
+obj-$(CONFIG_MT8366_POWER_DOMAIN) += mt8366-power-domain.o
 obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
 obj-$(CONFIG_QCOM_RPMH_POWER_DOMAIN) += qcom-rpmhpd.o
 obj-$(CONFIG_RENESAS_R8A78000_POWER_DOMAIN) += renesas-r8a78000-power-domain.o
diff --git a/drivers/power/domain/mt8366-power-domain.c b/drivers/power/domain/mt8366-power-domain.c
new file mode 100644
index 00000000000..d40cf1849bd
--- /dev/null
+++ b/drivers/power/domain/mt8366-power-domain.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 MediaTek Inc.
+ * Author: Irving-ch Lin <irving-ch.lin@mediatek.com>
+ */
+
+#include <dm.h>
+#include <dt-bindings/power/mediatek,mt8366-power.h>
+#include <linux/bitops.h>
+
+#include "mtk-power-domain.h"
+
+#define MT8366_SPM_PWR_STATUS			0x16c
+#define MT8366_SPM_PWR_STATUS_2ND		0x170
+
+#define MT8366_TOP_AXI_PROT_EN_STA1		0x0228
+#define MT8366_TOP_AXI_PROT_EN_STA1_1		0x0258
+#define MT8366_TOP_AXI_PROT_EN_SET		0x02a0
+#define MT8366_TOP_AXI_PROT_EN_CLR		0x02a4
+#define MT8366_TOP_AXI_PROT_EN_1_SET		0x02a8
+#define MT8366_TOP_AXI_PROT_EN_1_CLR		0x02ac
+#define MT8366_TOP_AXI_PROT_EN_MM_SET		0x02d4
+#define MT8366_TOP_AXI_PROT_EN_MM_CLR		0x02d8
+#define MT8366_TOP_AXI_PROT_EN_MM_STA1		0x02ec
+#define MT8366_TOP_AXI_PROT_EN_SET_2		0x0714
+#define MT8366_TOP_AXI_PROT_EN_CLR_2		0x0718
+#define MT8366_TOP_AXI_PROT_EN_STA1_2		0x0724
+#define MT8366_TOP_AXI_PROT_EN_ADSP_SET		0x0758
+#define MT8366_TOP_AXI_PROT_EN_ADSP_CLR		0x075c
+#define MT8366_TOP_AXI_PROT_EN_STA1_ADSP	0x0764
+
+#define MT8366_TOP_AXI_PROT_EN_CONN		(BIT(13) | BIT(18))
+#define MT8366_TOP_AXI_PROT_EN_CONN_2ND		(BIT(14))
+#define MT8366_TOP_AXI_PROT_EN_1_CONN		(BIT(10))
+#define MT8366_TOP_AXI_PROT_EN_1_MFG1		(BIT(21))
+#define MT8366_TOP_AXI_PROT_EN_2_MFG1		(BIT(5) | BIT(6))
+#define MT8366_TOP_AXI_PROT_EN_MFG1		(BIT(21) | BIT(22))
+#define MT8366_TOP_AXI_PROT_EN_2_MFG1_2ND	(BIT(7))
+#define MT8366_TOP_AXI_PROT_EN_MM_VDEC		(BIT(24))
+#define MT8366_TOP_AXI_PROT_EN_MM_VDEC_2ND	(BIT(25))
+#define MT8366_TOP_AXI_PROT_EN_MM_VENC		(BIT(26))
+#define MT8366_TOP_AXI_PROT_EN_MM_VENC_2ND	(BIT(27))
+#define MT8366_TOP_AXI_PROT_EN_2_AUDIO		(BIT(3))
+#define MT8366_TOP_AXI_PROT_EN_2_AUDIO_ACK	(BIT(4) | BIT(10) | BIT(13))
+#define MT8366_TOP_AXI_PROT_EN_MM_CAM		(BIT(0) | BIT(2))
+#define MT8366_TOP_AXI_PROT_EN_MM_CAM_2ND	(BIT(1) | BIT(3))
+
+static const struct mtk_scp_domain_data mt8366_scp_domain[] = {
+	[MT8366_POWER_DOMAIN_CONN] = {
+		.sta_mask = BIT(0),
+		.ctl_offs = 0x304,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.bp_infracfg = {
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_CONN,
+					MT8366_TOP_AXI_PROT_EN_SET,
+					MT8366_TOP_AXI_PROT_EN_CLR,
+					MT8366_TOP_AXI_PROT_EN_STA1),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_CONN_2ND,
+					MT8366_TOP_AXI_PROT_EN_SET,
+					MT8366_TOP_AXI_PROT_EN_CLR,
+					MT8366_TOP_AXI_PROT_EN_STA1),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_1_CONN,
+					MT8366_TOP_AXI_PROT_EN_1_SET,
+					MT8366_TOP_AXI_PROT_EN_1_CLR,
+					MT8366_TOP_AXI_PROT_EN_STA1_1),
+		},
+	},
+	[MT8366_POWER_DOMAIN_MFG0] = {
+		.sta_mask = BIT(1),
+		.ctl_offs = 0x308,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_MFG1] = {
+		.sta_mask = BIT(2),
+		.ctl_offs = 0x30c,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_1_MFG1,
+					MT8366_TOP_AXI_PROT_EN_1_SET,
+					MT8366_TOP_AXI_PROT_EN_1_CLR,
+					MT8366_TOP_AXI_PROT_EN_STA1_1),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_2_MFG1,
+					MT8366_TOP_AXI_PROT_EN_SET_2,
+					MT8366_TOP_AXI_PROT_EN_CLR_2,
+					MT8366_TOP_AXI_PROT_EN_STA1_2),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_MFG1,
+					MT8366_TOP_AXI_PROT_EN_SET,
+					MT8366_TOP_AXI_PROT_EN_CLR,
+					MT8366_TOP_AXI_PROT_EN_STA1),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_2_MFG1_2ND,
+					MT8366_TOP_AXI_PROT_EN_SET_2,
+					MT8366_TOP_AXI_PROT_EN_CLR_2,
+					MT8366_TOP_AXI_PROT_EN_STA1_2),
+		},
+	},
+	[MT8366_POWER_DOMAIN_MFG2] = {
+		.sta_mask = BIT(3),
+		.ctl_offs = 0x310,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_MFG3] = {
+		.sta_mask = BIT(4),
+		.ctl_offs = 0x314,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_VDEC] = {
+		.sta_mask = BIT(23),
+		.ctl_offs = 0x340,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_MM_VDEC,
+					MT8366_TOP_AXI_PROT_EN_MM_SET,
+					MT8366_TOP_AXI_PROT_EN_MM_CLR,
+					MT8366_TOP_AXI_PROT_EN_MM_STA1),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_MM_VDEC_2ND,
+					MT8366_TOP_AXI_PROT_EN_MM_SET,
+					MT8366_TOP_AXI_PROT_EN_MM_CLR,
+					MT8366_TOP_AXI_PROT_EN_MM_STA1),
+		},
+	},
+	[MT8366_POWER_DOMAIN_VENC] = {
+		.sta_mask = BIT(24),
+		.ctl_offs = 0x348,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_MM_VENC,
+					MT8366_TOP_AXI_PROT_EN_MM_SET,
+					MT8366_TOP_AXI_PROT_EN_MM_CLR,
+					MT8366_TOP_AXI_PROT_EN_MM_STA1),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_MM_VENC_2ND,
+					MT8366_TOP_AXI_PROT_EN_MM_SET,
+					MT8366_TOP_AXI_PROT_EN_MM_CLR,
+					MT8366_TOP_AXI_PROT_EN_MM_STA1),
+		},
+	},
+	[MT8366_POWER_DOMAIN_AUDIO] = {
+		.sta_mask = BIT(7),
+		.ctl_offs = 0x358,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR_IGN_STA_MASK(MT8366_TOP_AXI_PROT_EN_2_AUDIO,
+						 MT8366_TOP_AXI_PROT_EN_2_AUDIO_ACK,
+						 MT8366_TOP_AXI_PROT_EN_ADSP_SET,
+						 MT8366_TOP_AXI_PROT_EN_ADSP_CLR,
+						 MT8366_TOP_AXI_PROT_EN_STA1_ADSP),
+		},
+	},
+	[MT8366_POWER_DOMAIN_CAM] = {
+		.sta_mask = BIT(13),
+		.ctl_offs = 0x35c,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_MM_CAM,
+					MT8366_TOP_AXI_PROT_EN_MM_SET,
+					MT8366_TOP_AXI_PROT_EN_MM_CLR,
+					MT8366_TOP_AXI_PROT_EN_MM_STA1),
+			BUS_PROT_WR_IGN(MT8366_TOP_AXI_PROT_EN_MM_CAM_2ND,
+					MT8366_TOP_AXI_PROT_EN_MM_SET,
+					MT8366_TOP_AXI_PROT_EN_MM_CLR,
+					MT8366_TOP_AXI_PROT_EN_MM_STA1),
+		},
+	},
+	[MT8366_POWER_DOMAIN_CAM_RAWA] = {
+		.sta_mask = BIT(14),
+		.ctl_offs = 0x360,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_DISP] = {
+		.sta_mask = BIT(19),
+		.ctl_offs = 0x3f0,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_DP_TX] = {
+		.sta_mask = BIT(9),
+		.ctl_offs = 0x3ac,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_PCIE] = {
+		.sta_mask = BIT(12),
+		.ctl_offs = 0x3d4,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_ISP_IMG1] = {
+		.sta_mask = BIT(15),
+		.ctl_offs = 0x3e0,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_ISP_IMG2] = {
+		.sta_mask = BIT(16),
+		.ctl_offs = 0x3e4,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_ISP_IPE] = {
+		.sta_mask = BIT(17),
+		.ctl_offs = 0x3e8,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_MMLSYS_SHUTDOWN] = {
+		.sta_mask = BIT(18),
+		.ctl_offs = 0x3ec,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_EPD] = {
+		.sta_mask = BIT(20),
+		.ctl_offs = 0x3f4,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8366_POWER_DOMAIN_CSI_RX] = {
+		.sta_mask = BIT(25),
+		.ctl_offs = 0x408,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+	},
+	[MT8366_POWER_DOMAIN_VADSP_AO] = {
+		.sta_mask = BIT(28),
+		.ctl_offs = 0x414,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+	},
+	[MT8366_POWER_DOMAIN_VADSP_INFRA] = {
+		.sta_mask = BIT(27),
+		.ctl_offs = 0x410,
+		.pwr_sta_offs = MT8366_SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = MT8366_SPM_PWR_STATUS_2ND,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+};
+
+MTK_SCP_SOC_DATA(mt8366, mt8366_scp_domain);
+
+static const struct udevice_id mt8366_power_domain_ids[] = {
+	{
+		.compatible = "mediatek,mt8366-power-controller",
+		.data = (ulong)&mt8366_scp_soc_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(mt8366_power_domain) = {
+	.name = "mt8366_power_domain",
+	.id = UCLASS_POWER_DOMAIN,
+	.ops = &mtk_power_domain_ops,
+	.probe = mtk_power_controller_probe,
+	.of_match = mt8366_power_domain_ids,
+	.priv_auto = sizeof(struct mtk_scpsys),
+};
diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c
index 9eef58d2d57..8696ac21245 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -47,6 +47,7 @@ static int _scpsys_bus_protect_enable(const struct mtk_scpsys_bus_prot_data *bpd
 				      void __iomem *reg)
 {
 	u32 val = 0, mask = bpd->bus_prot_mask;
+	u32 sta_mask = bpd->bus_prot_sta_mask;
 
 	if (!mask)
 		return 0;
@@ -56,13 +57,15 @@ static int _scpsys_bus_protect_enable(const struct mtk_scpsys_bus_prot_data *bpd
 	else
 		writel(mask, reg + bpd->bus_prot_set);
 
-	return readl_poll_timeout(reg + bpd->bus_prot_sta, val, (val & mask) == mask, 1000);
+	return readl_poll_timeout(reg + bpd->bus_prot_sta, val,
+				  (val & sta_mask) == sta_mask, 1000);
 }
 
 static int _scpsys_bus_protect_disable(const struct mtk_scpsys_bus_prot_data *bpd,
 				       void __iomem *reg)
 {
 	u32 val = 0, mask = bpd->bus_prot_mask;
+	u32 sta_mask = bpd->bus_prot_sta_mask;
 
 	if (!mask)
 		return 0;
@@ -75,7 +78,8 @@ static int _scpsys_bus_protect_disable(const struct mtk_scpsys_bus_prot_data *bp
 	if (bpd->ignore_clr_ack)
 		return 0;
 
-	return readl_poll_timeout(reg + bpd->bus_prot_sta, val, !(val & mask), 1000);
+	return readl_poll_timeout(reg + bpd->bus_prot_sta, val,
+				  !(val & sta_mask), 1000);
 }
 
 static int scpsys_bus_protect_enable(const struct mtk_scpsys_bus_prot_data *bpd,
@@ -368,11 +372,6 @@ static int mtk_scpsys_add_one_domain(struct udevice *dev, ofnode node, int paren
 			return PTR_ERR(regmap);
 
 		domain->infracfg = regmap_get_range(regmap, 0);
-
-		/* enable Infra DCM */
-		if (domain->infracfg)
-			setbits_le32(domain->infracfg + INFRA_TOPDCM_CTRL,
-				     DCM_TOP_EN);
 	}
 
 	num_clks = ofnode_read_string_count(node, "clock-names");
diff --git a/drivers/power/domain/mtk-power-domain.h b/drivers/power/domain/mtk-power-domain.h
index 5bf0ca850ec..09f9fb3e5e9 100644
--- a/drivers/power/domain/mtk-power-domain.h
+++ b/drivers/power/domain/mtk-power-domain.h
@@ -68,6 +68,7 @@ struct mtk_scpsys_bus_prot_data {
 	u32 bus_prot_mask;
 	u32 bus_prot_set;
 	u32 bus_prot_clr;
+	u32 bus_prot_sta_mask;
 	u32 bus_prot_sta;
 	bool bus_prot_reg_update;
 	bool ignore_clr_ack;
@@ -111,17 +112,27 @@ struct mtk_scpsys {
 	struct mtk_scp_domain *domains;
 };
 
-#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) {	\
+#define _BUS_PROT(_mask, _set, _clr, _sta_mask, _sta, _update, _ignore) { \
 	.bus_prot_mask = (_mask),				\
 	.bus_prot_set = (_set),					\
 	.bus_prot_clr = (_clr),					\
+	.bus_prot_sta_mask = (_sta_mask),			\
 	.bus_prot_sta = (_sta),					\
 	.bus_prot_reg_update = (_update),			\
 	.ignore_clr_ack = (_ignore),				\
 }
 
 #define BUS_PROT_WR(_mask, _set, _clr, _sta)			\
-	_BUS_PROT(_mask, _set, _clr, _sta, false, false)
+	_BUS_PROT(_mask, _set, _clr, _mask, _sta, false, false)
+
+#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta)		\
+	_BUS_PROT(_mask, _set, _clr, _mask, _sta, false, true)
+
+#define BUS_PROT_WR_STA_MASK(_mask, _sta_mask, _set, _clr, _sta) \
+	_BUS_PROT(_mask, _set, _clr, _sta_mask, _sta, false, false)
+
+#define BUS_PROT_WR_IGN_STA_MASK(_mask, _sta_mask, _set, _clr, _sta) \
+	_BUS_PROT(_mask, _set, _clr, _sta_mask, _sta, false, true)
 
 int mtk_scpsys_probe(struct udevice *dev);
 int mtk_power_controller_probe(struct udevice *dev);
diff --git a/drivers/video/himax-hx8394.c b/drivers/video/himax-hx8394.c
index cb7f93e9c99..1107070bd1a 100644
--- a/drivers/video/himax-hx8394.c
+++ b/drivers/video/himax-hx8394.c
@@ -31,59 +31,51 @@ static const struct display_timing default_timing = {
 	.flags			= DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
 };
 
-#define dsi_dcs_write_seq(device, seq...) do {					\
-		static const u8 d[] = { seq };					\
-		int ret;							\
-		ret = mipi_dsi_dcs_write_buffer(device, d, ARRAY_SIZE(d));	\
-		if (ret < 0)							\
-			return ret;						\
-	} while (0)
-
 static int hx8394_init_sequence(struct udevice *dev)
 {
 	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
 	struct mipi_dsi_device *device = plat->device;
 	int ret;
 
-	dsi_dcs_write_seq(device, 0xb9, 0xff, 0x83, 0x94);
-	dsi_dcs_write_seq(device, 0xb1, 0x48, 0x11, 0x71, 0x09, 0x32, 0x24,
-			  0x71, 0x31, 0x55, 0x30);
-	dsi_dcs_write_seq(device, 0xba, 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
-	dsi_dcs_write_seq(device, 0xb2, 0x00, 0x80, 0x78, 0x0c, 0x07);
-	dsi_dcs_write_seq(device, 0xb4, 0x12, 0x63, 0x12, 0x63, 0x12, 0x63,
-			  0x01, 0x0c, 0x7c, 0x55, 0x00, 0x3f, 0x12, 0x6b, 0x12,
-			  0x6b, 0x12, 0x6b, 0x01, 0x0c, 0x7c);
-	dsi_dcs_write_seq(device, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c,
-			  0x00, 0x00, 0x32, 0x10, 0x09, 0x00, 0x09, 0x32, 0x15,
-			  0xad, 0x05, 0xad, 0x32, 0x00, 0x00, 0x00, 0x00, 0x37,
-			  0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 0x00, 0x0c, 0x40);
-	dsi_dcs_write_seq(device, 0xd5, 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b,
-			  0x1a, 0x1a, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
-			  0x07, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x24, 0x25, 0x18,
-			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-			  0x18, 0x18);
-	dsi_dcs_write_seq(device, 0xd6, 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b,
-			  0x1a, 0x1a, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
-			  0x00, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x18,
-			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-			  0x18, 0x18);
-	dsi_dcs_write_seq(device, 0xe0, 0x00, 0x04, 0x0c, 0x12, 0x14, 0x18,
-			  0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b,
-			  0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49,
-			  0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00, 0x04, 0x0c, 0x11,
-			  0x13, 0x17, 0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54,
-			  0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a,
-			  0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f);
-	dsi_dcs_write_seq(device, 0xcc, 0x0b);
-	dsi_dcs_write_seq(device, 0xc0, 0x1f, 0x31);
-	dsi_dcs_write_seq(device, 0xb6, 0x7d, 0x7d);
-	dsi_dcs_write_seq(device, 0xd4, 0x02);
-	dsi_dcs_write_seq(device, 0xbd, 0x01);
-	dsi_dcs_write_seq(device, 0xb1, 0x00);
-	dsi_dcs_write_seq(device, 0xbd, 0x00);
-	dsi_dcs_write_seq(device, 0xc6, 0xed);
+	mipi_dsi_dcs_write_seq(device, 0xb9, 0xff, 0x83, 0x94);
+	mipi_dsi_dcs_write_seq(device, 0xb1, 0x48, 0x11, 0x71, 0x09, 0x32, 0x24,
+			       0x71, 0x31, 0x55, 0x30);
+	mipi_dsi_dcs_write_seq(device, 0xba, 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
+	mipi_dsi_dcs_write_seq(device, 0xb2, 0x00, 0x80, 0x78, 0x0c, 0x07);
+	mipi_dsi_dcs_write_seq(device, 0xb4, 0x12, 0x63, 0x12, 0x63, 0x12, 0x63,
+			       0x01, 0x0c, 0x7c, 0x55, 0x00, 0x3f, 0x12, 0x6b, 0x12,
+			       0x6b, 0x12, 0x6b, 0x01, 0x0c, 0x7c);
+	mipi_dsi_dcs_write_seq(device, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c,
+			       0x00, 0x00, 0x32, 0x10, 0x09, 0x00, 0x09, 0x32, 0x15,
+			       0xad, 0x05, 0xad, 0x32, 0x00, 0x00, 0x00, 0x00, 0x37,
+			       0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 0x00, 0x0c, 0x40);
+	mipi_dsi_dcs_write_seq(device, 0xd5, 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b,
+			       0x1a, 0x1a, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
+			       0x07, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x24, 0x25, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			       0x18, 0x18);
+	mipi_dsi_dcs_write_seq(device, 0xd6, 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b,
+			       0x1a, 0x1a, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
+			       0x00, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			       0x18, 0x18);
+	mipi_dsi_dcs_write_seq(device, 0xe0, 0x00, 0x04, 0x0c, 0x12, 0x14, 0x18,
+			       0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b,
+			       0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49,
+			       0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00, 0x04, 0x0c, 0x11,
+			       0x13, 0x17, 0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54,
+			       0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a,
+			       0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f);
+	mipi_dsi_dcs_write_seq(device, 0xcc, 0x0b);
+	mipi_dsi_dcs_write_seq(device, 0xc0, 0x1f, 0x31);
+	mipi_dsi_dcs_write_seq(device, 0xb6, 0x7d, 0x7d);
+	mipi_dsi_dcs_write_seq(device, 0xd4, 0x02);
+	mipi_dsi_dcs_write_seq(device, 0xbd, 0x01);
+	mipi_dsi_dcs_write_seq(device, 0xb1, 0x00);
+	mipi_dsi_dcs_write_seq(device, 0xbd, 0x00);
+	mipi_dsi_dcs_write_seq(device, 0xc6, 0xed);
 
 	ret = mipi_dsi_dcs_exit_sleep_mode(device);
 	if (ret)
diff --git a/drivers/video/hitachi-tx10d07vm0baa.c b/drivers/video/hitachi-tx10d07vm0baa.c
index 95b2f7bfc41..9e800c324b4 100644
--- a/drivers/video/hitachi-tx10d07vm0baa.c
+++ b/drivers/video/hitachi-tx10d07vm0baa.c
@@ -35,28 +35,20 @@ static struct display_timing default_timing = {
 	.vsync_len.typ		= 4,
 };
 
-#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
-		static const u8 b[] = { cmd, seq };			\
-		int ret;						\
-		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
-		if (ret < 0)						\
-			return ret;					\
-	} while (0)
-
 static int hitachi_tx10d07vm0baa_enable_backlight(struct udevice *dev)
 {
 	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
 	struct mipi_dsi_device *dsi = plat->device;
 	int ret;
 
-	dsi_generic_write_seq(dsi, MIPI_DCS_SET_PARTIAL_AREA, 0x00,
-			      0x00, 0x03, 0x1f);
-	dsi_generic_write_seq(dsi, MIPI_DCS_SET_SCROLL_AREA, 0x00,
-			      0x00, 0x03, 0x20, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_AREA, 0x00,
+			       0x00, 0x03, 0x1f);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_SCROLL_AREA, 0x00,
+			       0x00, 0x03, 0x20, 0x00, 0x00);
 
-	dsi_generic_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x0a);
-	dsi_generic_write_seq(dsi, MIPI_DCS_SET_SCROLL_START, 0x00,
-			      0x00);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x0a);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_SCROLL_START, 0x00,
+			       0x00);
 
 	ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT);
 	if (ret) {
@@ -70,59 +62,59 @@ static int hitachi_tx10d07vm0baa_enable_backlight(struct udevice *dev)
 		return ret;
 	}
 
-	dsi_generic_write_seq(dsi, 0x71, 0x00);		/* Ex_Vsync_en */
-
-	dsi_generic_write_seq(dsi, 0xb2, 0x00);		/* VCSEL */
-	dsi_generic_write_seq(dsi, 0xb4, 0xaa);		/* setvgmpm */
-	dsi_generic_write_seq(dsi, 0xb5, 0x33);		/* rbias1 */
-	dsi_generic_write_seq(dsi, 0xb6, 0x03);		/* rbias2 */
-
-	dsi_generic_write_seq(dsi, 0xb7, 0x1a, 0x33, 0x03, 0x03,
-			      0x03, 0x00, 0x00, 0x01, 0x02, 0x00,
-			      0x00, 0x04, 0x00, 0x01, 0x01, 0x01);	/* set_ddvdhp */
-	dsi_generic_write_seq(dsi, 0xb8, 0x1c, 0x53, 0x03, 0x03,
-			      0x00, 0x01, 0x02, 0x00, 0x00, 0x04,
-			      0x00, 0x01, 0x01);			/* set_ddvdhm */
-
-	dsi_generic_write_seq(dsi, 0xb9, 0x0a, 0x01, 0x01, 0x00,
-			      0x00, 0x00, 0x02, 0x00, 0x02, 0x01);	/* set_vgh */
-	dsi_generic_write_seq(dsi, 0xba, 0x0f, 0x01, 0x01, 0x00,
-			      0x00, 0x00, 0x02, 0x00, 0x02, 0x01);	/* set_vgl */
-	dsi_generic_write_seq(dsi, 0xbb, 0x00, 0x00, 0x00, 0x00,
-			      0x01, 0x02, 0x01);			/* set_vcl */
-
-	dsi_generic_write_seq(dsi, 0xc1, 0x01);		/* number of lines */
-	dsi_generic_write_seq(dsi, 0xc2, 0x08);		/* number of fp lines */
-	dsi_generic_write_seq(dsi, 0xc3, 0x04);		/* gateset(1) */
-	dsi_generic_write_seq(dsi, 0xc4, 0x4c);		/* 1h period */
-	dsi_generic_write_seq(dsi, 0xc5, 0x03);		/* source precharge */
-	dsi_generic_write_seq(dsi, 0xc6, 0xc4, 0x04);	/* source precharge timing */
-	dsi_generic_write_seq(dsi, 0xc7, 0x00);		/* source level */
-	dsi_generic_write_seq(dsi, 0xc8, 0x02);		/* number of bp lines */
-	dsi_generic_write_seq(dsi, 0xc9, 0x10);		/* gateset(2) */
-	dsi_generic_write_seq(dsi, 0xca, 0x04, 0x04);	/* gateset(3) */
-	dsi_generic_write_seq(dsi, 0xcb, 0x03);		/* gateset(4) */
-	dsi_generic_write_seq(dsi, 0xcc, 0x12);		/* gateset(5) */
-	dsi_generic_write_seq(dsi, 0xcd, 0x12);		/* gateset(6) */
-	dsi_generic_write_seq(dsi, 0xce, 0x30);		/* gateset(7) */
-	dsi_generic_write_seq(dsi, 0xcf, 0x30);		/* gateset(8) */
-	dsi_generic_write_seq(dsi, 0xd0, 0x40);		/* gateset(9) */
-	dsi_generic_write_seq(dsi, 0xd1, 0x22);		/* flhw */
-	dsi_generic_write_seq(dsi, 0xd2, 0x22);		/* vckhw */
-	dsi_generic_write_seq(dsi, 0xd3, 0x04);		/* flt */
-	dsi_generic_write_seq(dsi, 0xd4, 0x14);		/* tctrl */
-	dsi_generic_write_seq(dsi, 0xd6, 0x02);		/* dotinv */
-	dsi_generic_write_seq(dsi, 0xd7, 0x00);		/* on/off sequence period */
-
-	dsi_generic_write_seq(dsi, 0xd8, 0x01, 0x05, 0x06, 0x0d,
-			      0x18, 0x09, 0x22, 0x23, 0x00);		/* ponseqa */
-	dsi_generic_write_seq(dsi, 0xd9, 0x24, 0x01);			/* ponseqb */
-	dsi_generic_write_seq(dsi, 0xde, 0x09, 0x0f, 0x21, 0x12,
-			      0x04);					/* ponseqc */
-
-	dsi_generic_write_seq(dsi, 0xdf, 0x02, 0x06, 0x06, 0x06,
-			      0x06, 0x00);				/* pofseqa */
-	dsi_generic_write_seq(dsi, 0xe0, 0x01);				/* pofseqb */
+	mipi_dsi_dcs_write_seq(dsi, 0x71, 0x00);		/* Ex_Vsync_en */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x00);		/* VCSEL */
+	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0xaa);		/* setvgmpm */
+	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x33);		/* rbias1 */
+	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x03);		/* rbias2 */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x1a, 0x33, 0x03, 0x03,
+			       0x03, 0x00, 0x00, 0x01, 0x02, 0x00,
+			       0x00, 0x04, 0x00, 0x01, 0x01, 0x01);	/* set_ddvdhp */
+	mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x1c, 0x53, 0x03, 0x03,
+			       0x00, 0x01, 0x02, 0x00, 0x00, 0x04,
+			       0x00, 0x01, 0x01);			/* set_ddvdhm */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x0a, 0x01, 0x01, 0x00,
+			       0x00, 0x00, 0x02, 0x00, 0x02, 0x01);	/* set_vgh */
+	mipi_dsi_dcs_write_seq(dsi, 0xba, 0x0f, 0x01, 0x01, 0x00,
+			       0x00, 0x00, 0x02, 0x00, 0x02, 0x01);	/* set_vgl */
+	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x00, 0x00, 0x00, 0x00,
+			       0x01, 0x02, 0x01);			/* set_vcl */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x01);		/* number of lines */
+	mipi_dsi_dcs_write_seq(dsi, 0xc2, 0x08);		/* number of fp lines */
+	mipi_dsi_dcs_write_seq(dsi, 0xc3, 0x04);		/* gateset(1) */
+	mipi_dsi_dcs_write_seq(dsi, 0xc4, 0x4c);		/* 1h period */
+	mipi_dsi_dcs_write_seq(dsi, 0xc5, 0x03);		/* source precharge */
+	mipi_dsi_dcs_write_seq(dsi, 0xc6, 0xc4, 0x04);	/* source precharge timing */
+	mipi_dsi_dcs_write_seq(dsi, 0xc7, 0x00);		/* source level */
+	mipi_dsi_dcs_write_seq(dsi, 0xc8, 0x02);		/* number of bp lines */
+	mipi_dsi_dcs_write_seq(dsi, 0xc9, 0x10);		/* gateset(2) */
+	mipi_dsi_dcs_write_seq(dsi, 0xca, 0x04, 0x04);	/* gateset(3) */
+	mipi_dsi_dcs_write_seq(dsi, 0xcb, 0x03);		/* gateset(4) */
+	mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x12);		/* gateset(5) */
+	mipi_dsi_dcs_write_seq(dsi, 0xcd, 0x12);		/* gateset(6) */
+	mipi_dsi_dcs_write_seq(dsi, 0xce, 0x30);		/* gateset(7) */
+	mipi_dsi_dcs_write_seq(dsi, 0xcf, 0x30);		/* gateset(8) */
+	mipi_dsi_dcs_write_seq(dsi, 0xd0, 0x40);		/* gateset(9) */
+	mipi_dsi_dcs_write_seq(dsi, 0xd1, 0x22);		/* flhw */
+	mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x22);		/* vckhw */
+	mipi_dsi_dcs_write_seq(dsi, 0xd3, 0x04);		/* flt */
+	mipi_dsi_dcs_write_seq(dsi, 0xd4, 0x14);		/* tctrl */
+	mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x02);		/* dotinv */
+	mipi_dsi_dcs_write_seq(dsi, 0xd7, 0x00);		/* on/off sequence period */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xd8, 0x01, 0x05, 0x06, 0x0d,
+			       0x18, 0x09, 0x22, 0x23, 0x00);		/* ponseqa */
+	mipi_dsi_dcs_write_seq(dsi, 0xd9, 0x24, 0x01);			/* ponseqb */
+	mipi_dsi_dcs_write_seq(dsi, 0xde, 0x09, 0x0f, 0x21, 0x12,
+			       0x04);					/* ponseqc */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x02, 0x06, 0x06, 0x06,
+			       0x06, 0x00);				/* pofseqa */
+	mipi_dsi_dcs_write_seq(dsi, 0xe0, 0x01);				/* pofseqb */
 
 	ret = mipi_dsi_dcs_set_display_brightness(dsi, 0xff);
 	if (ret) {
@@ -130,32 +122,32 @@ static int hitachi_tx10d07vm0baa_enable_backlight(struct udevice *dev)
 		return ret;
 	}
 
-	dsi_generic_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x40);
-
-	dsi_generic_write_seq(dsi, 0xe2, 0x00, 0x00);		/* cabc pwm */
-	dsi_generic_write_seq(dsi, 0xe3, 0x03);			/* cabc */
-	dsi_generic_write_seq(dsi, 0xe4, 0x66, 0x7b, 0x90, 0xa5,
-			      0xbb, 0xc7, 0xe1, 0xe5);		/* cabc brightness */
-	dsi_generic_write_seq(dsi, 0xe5, 0xc5, 0xc5, 0xc9, 0xc9,
-			      0xd1, 0xe1, 0xf1, 0xfe);		/* cabc brightness */
-	dsi_generic_write_seq(dsi, 0xe7, 0x2a);			/* cabc */
-	dsi_generic_write_seq(dsi, 0xe8, 0x00);			/* brt_rev */
-	dsi_generic_write_seq(dsi, 0xe9, 0x00);			/* tefreq */
-
-	dsi_generic_write_seq(dsi, 0xea, 0x01);			/* high speed ram */
-
-	dsi_generic_write_seq(dsi, 0xeb, 0x00, 0x33, 0x0e, 0x15,
-			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting r pos */
-	dsi_generic_write_seq(dsi, 0xec, 0x00, 0x33, 0x0e, 0x15,
-			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting r neg */
-	dsi_generic_write_seq(dsi, 0xed, 0x00, 0x33, 0x0e, 0x15,
-			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting g pos */
-	dsi_generic_write_seq(dsi, 0xee, 0x00, 0x33, 0x0e, 0x15,
-			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting g neg */
-	dsi_generic_write_seq(dsi, 0xef, 0x00, 0x33, 0x0e, 0x15,
-			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting b pos */
-	dsi_generic_write_seq(dsi, 0xf0, 0x00, 0x33, 0x0e, 0x15,
-			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting b neg */
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x40);
+
+	mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x00, 0x00);		/* cabc pwm */
+	mipi_dsi_dcs_write_seq(dsi, 0xe3, 0x03);			/* cabc */
+	mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x66, 0x7b, 0x90, 0xa5,
+			       0xbb, 0xc7, 0xe1, 0xe5);		/* cabc brightness */
+	mipi_dsi_dcs_write_seq(dsi, 0xe5, 0xc5, 0xc5, 0xc9, 0xc9,
+			       0xd1, 0xe1, 0xf1, 0xfe);		/* cabc brightness */
+	mipi_dsi_dcs_write_seq(dsi, 0xe7, 0x2a);			/* cabc */
+	mipi_dsi_dcs_write_seq(dsi, 0xe8, 0x00);			/* brt_rev */
+	mipi_dsi_dcs_write_seq(dsi, 0xe9, 0x00);			/* tefreq */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xea, 0x01);			/* high speed ram */
+
+	mipi_dsi_dcs_write_seq(dsi, 0xeb, 0x00, 0x33, 0x0e, 0x15,
+			       0xb7, 0x78, 0x88, 0x0f);		/* gamma setting r pos */
+	mipi_dsi_dcs_write_seq(dsi, 0xec, 0x00, 0x33, 0x0e, 0x15,
+			       0xb7, 0x78, 0x88, 0x0f);		/* gamma setting r neg */
+	mipi_dsi_dcs_write_seq(dsi, 0xed, 0x00, 0x33, 0x0e, 0x15,
+			       0xb7, 0x78, 0x88, 0x0f);		/* gamma setting g pos */
+	mipi_dsi_dcs_write_seq(dsi, 0xee, 0x00, 0x33, 0x0e, 0x15,
+			       0xb7, 0x78, 0x88, 0x0f);		/* gamma setting g neg */
+	mipi_dsi_dcs_write_seq(dsi, 0xef, 0x00, 0x33, 0x0e, 0x15,
+			       0xb7, 0x78, 0x88, 0x0f);		/* gamma setting b pos */
+	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x00, 0x33, 0x0e, 0x15,
+			       0xb7, 0x78, 0x88, 0x0f);		/* gamma setting b neg */
 
 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 	if (ret) {
diff --git a/drivers/video/lg-lh400wv3-sd04.c b/drivers/video/lg-lh400wv3-sd04.c
index 0385b39867f..8e6b5d2d723 100644
--- a/drivers/video/lg-lh400wv3-sd04.c
+++ b/drivers/video/lg-lh400wv3-sd04.c
@@ -35,22 +35,14 @@ static struct display_timing default_timing = {
 	.vsync_len.typ		= 4,
 };
 
-#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
-		static const u8 b[] = { cmd, seq };			\
-		int ret;						\
-		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
-		if (ret < 0)						\
-			return ret;					\
-	} while (0)
-
 static int lg_lh400wv3_enable_backlight(struct udevice *dev)
 {
 	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
 	struct mipi_dsi_device *dsi = plat->device;
 	int ret;
 
-	dsi_generic_write_seq(dsi, MIPI_DCS_EXIT_INVERT_MODE);
-	dsi_generic_write_seq(dsi, MIPI_DCS_SET_TEAR_ON);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_EXIT_INVERT_MODE);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_TEAR_ON);
 
 	ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT |
 					    MIPI_DCS_PIXEL_FMT_24BIT << 4);
@@ -59,28 +51,28 @@ static int lg_lh400wv3_enable_backlight(struct udevice *dev)
 		return ret;
 	}
 
-	dsi_generic_write_seq(dsi, 0xb2, 0x00, 0xc8);
-	dsi_generic_write_seq(dsi, 0xb3, 0x00);
-	dsi_generic_write_seq(dsi, 0xb4, 0x04);
-	dsi_generic_write_seq(dsi, 0xb5, 0x42, 0x10, 0x10, 0x00, 0x20);
-	dsi_generic_write_seq(dsi, 0xb6, 0x0b, 0x0f, 0x3c, 0x13, 0x13, 0xe8);
-	dsi_generic_write_seq(dsi, 0xb7, 0x4c, 0x06, 0x0c, 0x00, 0x00);
-
-	dsi_generic_write_seq(dsi, 0xc0, 0x01, 0x11);
-	dsi_generic_write_seq(dsi, 0xc3, 0x07, 0x03, 0x04, 0x04, 0x04);
-	dsi_generic_write_seq(dsi, 0xc4, 0x12, 0x24, 0x18, 0x18, 0x02, 0x49);
-	dsi_generic_write_seq(dsi, 0xc5, 0x65);
-	dsi_generic_write_seq(dsi, 0xc6, 0x41, 0x63);
-
-	dsi_generic_write_seq(dsi, 0xd0, 0x00, 0x46, 0x74, 0x32, 0x1d, 0x03, 0x51, 0x15, 0x04);
-	dsi_generic_write_seq(dsi, 0xd1, 0x00, 0x46, 0x74, 0x32, 0x1d, 0x03, 0x51, 0x15, 0x04);
-	dsi_generic_write_seq(dsi, 0xd2, 0x00, 0x46, 0x74, 0x32, 0x1f, 0x03, 0x51, 0x15, 0x04);
-	dsi_generic_write_seq(dsi, 0xd3, 0x00, 0x46, 0x74, 0x32, 0x1f, 0x03, 0x51, 0x15, 0x04);
-	dsi_generic_write_seq(dsi, 0xd4, 0x01, 0x46, 0x74, 0x25, 0x00, 0x03, 0x51, 0x15, 0x04);
-	dsi_generic_write_seq(dsi, 0xd5, 0x01, 0x46, 0x74, 0x25, 0x00, 0x03, 0x51, 0x15, 0x04);
-
-	dsi_generic_write_seq(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, 0x00, 0x00, 0x01, 0xdf);
-	dsi_generic_write_seq(dsi, MIPI_DCS_SET_PAGE_ADDRESS, 0x00, 0x00, 0x03, 0x1f);
+	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0xc8);
+	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x42, 0x10, 0x10, 0x00, 0x20);
+	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x0b, 0x0f, 0x3c, 0x13, 0x13, 0xe8);
+	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x4c, 0x06, 0x0c, 0x00, 0x00);
+
+	mipi_dsi_dcs_write_seq(dsi, 0xc0, 0x01, 0x11);
+	mipi_dsi_dcs_write_seq(dsi, 0xc3, 0x07, 0x03, 0x04, 0x04, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xc4, 0x12, 0x24, 0x18, 0x18, 0x02, 0x49);
+	mipi_dsi_dcs_write_seq(dsi, 0xc5, 0x65);
+	mipi_dsi_dcs_write_seq(dsi, 0xc6, 0x41, 0x63);
+
+	mipi_dsi_dcs_write_seq(dsi, 0xd0, 0x00, 0x46, 0x74, 0x32, 0x1d, 0x03, 0x51, 0x15, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xd1, 0x00, 0x46, 0x74, 0x32, 0x1d, 0x03, 0x51, 0x15, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x00, 0x46, 0x74, 0x32, 0x1f, 0x03, 0x51, 0x15, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xd3, 0x00, 0x46, 0x74, 0x32, 0x1f, 0x03, 0x51, 0x15, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xd4, 0x01, 0x46, 0x74, 0x25, 0x00, 0x03, 0x51, 0x15, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xd5, 0x01, 0x46, 0x74, 0x25, 0x00, 0x03, 0x51, 0x15, 0x04);
+
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, 0x00, 0x00, 0x01, 0xdf);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PAGE_ADDRESS, 0x00, 0x00, 0x03, 0x1f);
 
 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 	if (ret < 0) {
@@ -90,7 +82,7 @@ static int lg_lh400wv3_enable_backlight(struct udevice *dev)
 
 	mdelay(120);
 
-	dsi_generic_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START);
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START);
 
 	ret = mipi_dsi_dcs_set_display_on(dsi);
 	if (ret < 0) {
diff --git a/drivers/video/mot-panel.c b/drivers/video/mot-panel.c
index a9114957867..ee131133e1f 100644
--- a/drivers/video/mot-panel.c
+++ b/drivers/video/mot-panel.c
@@ -27,14 +27,6 @@ struct mot_panel_priv {
 	struct gpio_desc reset_gpio;
 };
 
-#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
-		static const u8 b[] = { cmd, seq };			\
-		int ret;						\
-		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
-		if (ret < 0)						\
-			return ret;					\
-	} while (0)
-
 static struct display_timing default_timing = {
 	.pixelclock.typ		= 38250000,
 	.hactive.typ		= 540,
@@ -51,7 +43,7 @@ static int mot_es2(struct mipi_dsi_device *dsi)
 {
 	int ret;
 
-	dsi_generic_write_seq(dsi, 0x55, 0x01);
+	mipi_dsi_dcs_write_seq(dsi, 0x55, 0x01);
 
 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 	if (ret < 0) {
@@ -60,45 +52,45 @@ static int mot_es2(struct mipi_dsi_device *dsi)
 	}
 	mdelay(120);
 
-	dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
-			      0x74, 0x29, 0x12, 0x15, 0x2f, 0x2f, 0x04);
-	dsi_generic_write_seq(dsi, 0xf8, 0x4b, 0x04, 0x10, 0x1a, 0x2c, 0x2c,
-			      0x2c, 0x2c, 0x14, 0x12);
+	mipi_dsi_dcs_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
+			       0x74, 0x29, 0x12, 0x15, 0x2f, 0x2f, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xf8, 0x4b, 0x04, 0x10, 0x1a, 0x2c, 0x2c,
+			       0x2c, 0x2c, 0x14, 0x12);
 
-	dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x00, 0x80, 0xc7, 0x00);
-	dsi_generic_write_seq(dsi, 0xb7, 0x66, 0xf6, 0x46, 0x9f, 0x90, 0x99,
-			      0xff, 0x80, 0x6d, 0x01);
+	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x00, 0x80, 0xc7, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x66, 0xf6, 0x46, 0x9f, 0x90, 0x99,
+			       0xff, 0x80, 0x6d, 0x01);
 
 	/* Gamma R */
-	dsi_generic_write_seq(dsi, 0xf9, 0x04);
-	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
-			      0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
-	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
-			      0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
+			       0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
+			       0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
 
 	/* Gamma G */
-	dsi_generic_write_seq(dsi, 0xf9, 0x02);
-	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
-			      0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
-	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
-			      0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x02);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
+			       0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
+			       0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
 
 	/* Gamma B */
-	dsi_generic_write_seq(dsi, 0xf9, 0x01);
-	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
-			      0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
-	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
-			      0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x01);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
+			       0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
+			       0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
 
 	/* Gamma W */
-	dsi_generic_write_seq(dsi, 0xf9, 0x20);
-	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
-			      0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
-	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
-			      0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x20);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
+			       0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
+			       0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
 
-	dsi_generic_write_seq(dsi, 0x53, 0x2c);
-	dsi_generic_write_seq(dsi, 0x35, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, 0x53, 0x2c);
+	mipi_dsi_dcs_write_seq(dsi, 0x35, 0x00);
 
 	return 0;
 }
@@ -107,9 +99,9 @@ static int __maybe_unused mot_es4(struct mipi_dsi_device *dsi)
 {
 	int ret;
 
-	dsi_generic_write_seq(dsi, 0xd2, 0x04, 0x53);
-	dsi_generic_write_seq(dsi, 0xd2, 0x05, 0x53);
-	dsi_generic_write_seq(dsi, 0x55, 0x01);
+	mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x04, 0x53);
+	mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x05, 0x53);
+	mipi_dsi_dcs_write_seq(dsi, 0x55, 0x01);
 
 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 	if (ret < 0) {
@@ -118,45 +110,45 @@ static int __maybe_unused mot_es4(struct mipi_dsi_device *dsi)
 	}
 	mdelay(120);
 
-	dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x0a, 0x80, 0xff, 0x00);
-	dsi_generic_write_seq(dsi, 0xb7, 0x7a, 0xf7, 0x4d, 0x91, 0x90, 0xb3,
-			      0xff, 0x80, 0x6d, 0x01);
-	dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
-			      0x74, 0x29, 0x12, 0x15, 0x37, 0x37, 0x04);
-	dsi_generic_write_seq(dsi, 0xf8, 0x0a, 0x04, 0x10, 0x2a, 0x35, 0x35,
-			      0x35, 0x35, 0x21, 0x1a);
+	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x0a, 0x80, 0xff, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x7a, 0xf7, 0x4d, 0x91, 0x90, 0xb3,
+			       0xff, 0x80, 0x6d, 0x01);
+	mipi_dsi_dcs_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
+			       0x74, 0x29, 0x12, 0x15, 0x37, 0x37, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xf8, 0x0a, 0x04, 0x10, 0x2a, 0x35, 0x35,
+			       0x35, 0x35, 0x21, 0x1a);
 
 	/* Gamma R */
-	dsi_generic_write_seq(dsi, 0xf9, 0x04);
-	dsi_generic_write_seq(dsi, 0xfa, 0x08, 0x1c, 0x1b, 0x0f, 0x0f, 0x0a,
-			      0x1e, 0x22, 0x27, 0x26, 0x07, 0x0d);
-	dsi_generic_write_seq(dsi, 0xfb, 0x08, 0x3c, 0x27, 0x0f, 0x0f, 0x0a,
-			      0x1e, 0x26, 0x31, 0x2f, 0x07, 0x0b);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x04);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x08, 0x1c, 0x1b, 0x0f, 0x0f, 0x0a,
+			       0x1e, 0x22, 0x27, 0x26, 0x07, 0x0d);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x08, 0x3c, 0x27, 0x0f, 0x0f, 0x0a,
+			       0x1e, 0x26, 0x31, 0x2f, 0x07, 0x0b);
 
 	/* Gamma G */
-	dsi_generic_write_seq(dsi, 0xf9, 0x02);
-	dsi_generic_write_seq(dsi, 0xfa, 0x30, 0x14, 0x0f, 0x00, 0x06, 0x02,
-			      0x1e, 0x22, 0x27, 0x27, 0x08, 0x10);
-	dsi_generic_write_seq(dsi, 0xfb, 0x30, 0x35, 0x0f, 0x00, 0x0a, 0x02,
-			      0x1c, 0x23, 0x31, 0x2f, 0x08, 0x0e);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x02);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x30, 0x14, 0x0f, 0x00, 0x06, 0x02,
+			       0x1e, 0x22, 0x27, 0x27, 0x08, 0x10);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x30, 0x35, 0x0f, 0x00, 0x0a, 0x02,
+			       0x1c, 0x23, 0x31, 0x2f, 0x08, 0x0e);
 
 	/* Gamma B */
-	dsi_generic_write_seq(dsi, 0xf9, 0x01);
-	dsi_generic_write_seq(dsi, 0xfa, 0x12, 0x1b, 0x26, 0x0e, 0x12, 0x0b,
-			      0x1e, 0x22, 0x27, 0x27, 0x06, 0x0c);
-	dsi_generic_write_seq(dsi, 0xfb, 0x12, 0x3b, 0x2c, 0x12, 0x12, 0x0e,
-			      0x1e, 0x26, 0x31, 0x2f, 0x06, 0x0d);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x01);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x12, 0x1b, 0x26, 0x0e, 0x12, 0x0b,
+			       0x1e, 0x22, 0x27, 0x27, 0x06, 0x0c);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x12, 0x3b, 0x2c, 0x12, 0x12, 0x0e,
+			       0x1e, 0x26, 0x31, 0x2f, 0x06, 0x0d);
 
 	/* Gamma W */
-	dsi_generic_write_seq(dsi, 0xf9, 0x20);
-	dsi_generic_write_seq(dsi, 0xfa, 0x37, 0x1b, 0x09, 0x01, 0x06, 0x04,
-			      0x19, 0x19, 0x22, 0x24, 0x04, 0x15);
-	dsi_generic_write_seq(dsi, 0xfb, 0x37, 0x3b, 0x17, 0x01, 0x0a, 0x04,
-			      0x19, 0x1d, 0x2c, 0x2c, 0x04, 0x13);
+	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x20);
+	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x37, 0x1b, 0x09, 0x01, 0x06, 0x04,
+			       0x19, 0x19, 0x22, 0x24, 0x04, 0x15);
+	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x37, 0x3b, 0x17, 0x01, 0x0a, 0x04,
+			       0x19, 0x1d, 0x2c, 0x2c, 0x04, 0x13);
 
-	dsi_generic_write_seq(dsi, 0x53, 0x2c);
-	dsi_generic_write_seq(dsi, 0x35, 0x00);
-	dsi_generic_write_seq(dsi, 0xc3, 0x01, 0x4e);
+	mipi_dsi_dcs_write_seq(dsi, 0x53, 0x2c);
+	mipi_dsi_dcs_write_seq(dsi, 0x35, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, 0xc3, 0x01, 0x4e);
 
 	return 0;
 }
@@ -167,9 +159,9 @@ static int mot_panel_enable_backlight(struct udevice *dev)
 	struct mipi_dsi_device *dsi = plat->device;
 	int ret;
 
-	dsi_generic_write_seq(dsi, 0xf0, 0x5a, 0x5a);
-	dsi_generic_write_seq(dsi, 0xf1, 0x5a, 0x5a);
-	dsi_generic_write_seq(dsi, 0xd0, 0x8e);
+	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq(dsi, 0xf1, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq(dsi, 0xd0, 0x8e);
 
 	ret = mot_es2(dsi);
 	if (ret)
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index 1470eaf4cab..c3b0bb380c4 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -8,6 +8,7 @@
 
 #include <dm.h>
 #include <backlight.h>
+#include <limits.h>
 #include <log.h>
 #include <malloc.h>
 #include <pwm.h>
@@ -17,6 +18,65 @@
 #include <power/regulator.h>
 
 /**
+ * build_interpolated_levels() - Build a linearly interpolated levels table
+ *
+ * Some "brightness-levels" tables only list a few anchor points and rely on
+ * "num-interpolated-steps" to fill in the values between them, so that a
+ * high resolution PWM duty cycle can be used without listing every value.
+ *
+ * @raw_levels: Anchor point values read from "brightness-levels"
+ * @count:	Number of anchor points in @raw_levels
+ * @num_steps:	Number of interpolated steps between each anchor point
+ * @levels:	Returns newly allocated table of (count - 1) * num_steps + 1
+ *		entries
+ * @num_levels: Returns the number of entries in @levels
+ * Return: 0 on success, -EINVAL if @count or @num_steps are invalid, -ENOMEM
+ *	   on allocation failure
+ */
+static int build_interpolated_levels(const u32 *raw_levels, u32 count,
+				     u32 num_steps, u32 **levels,
+				     u32 *num_levels)
+{
+	u64 count_out64;
+	u32 count_out, *table, i, x;
+
+	/*
+	 * num_steps must fit in the s32 divisor of div_s64(), and count_out64
+	 * must fit both u32 (it is stored as such) and the byte size passed
+	 * to malloc().
+	 */
+	if (count < 2 || num_steps == 0 || num_steps > S32_MAX)
+		return -EINVAL;
+
+	count_out64 = (u64)(count - 1) * num_steps + 1;
+	if (count_out64 > U32_MAX || count_out64 > SIZE_MAX / sizeof(u32))
+		return -EINVAL;
+
+	count_out = count_out64;
+
+	table = malloc(count_out * sizeof(u32));
+	if (!table)
+		return -ENOMEM;
+
+	for (i = 0; i < count - 1; i++) {
+		u32 x1 = i * num_steps;
+		u32 x2 = x1 + num_steps;
+		u32 y1 = raw_levels[i];
+		u32 y2 = raw_levels[i + 1];
+		s64 dy = (s64)y2 - y1;
+
+		for (x = x1; x < x2; x++)
+			table[x] = y1 + div_s64(dy * (x - x1), num_steps);
+	}
+
+	table[count_out - 1] = raw_levels[count - 1];
+	*levels = table;
+	*num_levels = count_out;
+
+	return 0;
+}
+
+/**
  * Private information for the PWM backlight
  *
  * If @num_levels is 0 then the levels are simple values with the backlight
@@ -49,7 +109,7 @@ struct pwm_backlight_priv {
 	 */
 	bool polarity;
 	u32 *levels;
-	int num_levels;
+	u32 num_levels;
 	uint default_level;
 	int cur_level;
 	uint min_level;
@@ -196,6 +256,7 @@ static int pwm_backlight_of_to_plat(struct udevice *dev)
 	struct ofnode_phandle_args args;
 	int index, ret, count, len;
 	const u32 *cell;
+	u32 num_steps;
 
 	log_debug("start\n");
 	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
@@ -232,20 +293,60 @@ static int pwm_backlight_of_to_plat(struct udevice *dev)
 	index = dev_read_u32_default(dev, "default-brightness-level", 255);
 	cell = dev_read_prop(dev, "brightness-levels", &len);
 	count = len / sizeof(u32);
-	if (cell && count > index) {
-		priv->levels = malloc(len);
-		if (!priv->levels)
+
+	/*
+	 * If present, "num-interpolated-steps" means the levels above are
+	 * just anchor points, and the actual table used for
+	 * default-brightness-level and PWM duty cycle is the interpolated
+	 * table built from those anchor points. Interpolating needs at
+	 * least two anchor points.
+	 */
+	num_steps = dev_read_u32_default(dev, "num-interpolated-steps", 0);
+
+	priv->default_level = index;
+	priv->max_level = 255;
+
+	if (cell && count >= (num_steps ? 2 : 1)) {
+		u32 *raw_levels;
+
+		raw_levels = malloc(len);
+		if (!raw_levels)
 			return log_ret(-ENOMEM);
-		ret = dev_read_u32_array(dev, "brightness-levels", priv->levels,
+
+		ret = dev_read_u32_array(dev, "brightness-levels", raw_levels,
 					 count);
-		if (ret)
+		if (ret) {
+			free(raw_levels);
 			return log_msg_ret("levels", ret);
-		priv->num_levels = count;
-		priv->default_level = priv->levels[index];
-		priv->max_level = priv->levels[count - 1];
-	} else {
-		priv->default_level = index;
-		priv->max_level = 255;
+		}
+
+		if (num_steps) {
+			ret = build_interpolated_levels(raw_levels, count, num_steps,
+							&priv->levels,
+							&priv->num_levels);
+			free(raw_levels);
+			if (ret)
+				return log_ret(ret);
+		} else {
+			priv->levels = raw_levels;
+			priv->num_levels = count;
+		}
+
+		if (index < priv->num_levels) {
+			priv->default_level = priv->levels[index];
+			priv->max_level = priv->levels[priv->num_levels - 1];
+		} else {
+			/*
+			 * default-brightness-level is out of range for the
+			 * table: fall back to raw 0-255 PWM scaling instead
+			 * of using the table at all.
+			 */
+			log_warning("default-brightness-level %d out of range for %u-entry brightness-levels table, ignoring table\n",
+				    index, priv->num_levels);
+			free(priv->levels);
+			priv->levels = NULL;
+			priv->num_levels = 0;
+		}
 	}
 	priv->cur_level = priv->default_level;
 	log_debug("done\n");
diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c
index 0954b04b62e..e4f563c09c5 100644
--- a/drivers/video/renesas-r69328.c
+++ b/drivers/video/renesas-r69328.c
@@ -40,18 +40,6 @@ struct renesas_r69328_priv {
 	struct gpio_desc reset_gpio;
 };
 
-static const u8 address_mode[] = {
-	MIPI_DCS_SET_ADDRESS_MODE
-};
-
-#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
-		static const u8 b[] = { cmd, seq };			\
-		int ret;						\
-		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
-		if (ret < 0)						\
-			return ret;					\
-	} while (0)
-
 static struct display_timing default_timing = {
 	.pixelclock.typ		= 68000000,
 	.hactive.typ		= 720,
@@ -70,8 +58,7 @@ static int renesas_r69328_enable_backlight(struct udevice *dev)
 	struct mipi_dsi_device *dsi = plat->device;
 	int ret;
 
-	mipi_dsi_dcs_write_buffer(dsi, address_mode,
-				  sizeof(address_mode));
+	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE);
 
 	ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT << 4);
 	if (ret < 0) {
@@ -88,35 +75,35 @@ static int renesas_r69328_enable_backlight(struct udevice *dev)
 	mdelay(100);
 
 	/* MACP Off */
-	dsi_generic_write_seq(dsi, R69328_MACP, 0x04);
-
-	dsi_generic_write_seq(dsi, R69328_POWER_SET, 0x14,
-			      0x1d, 0x21, 0x67, 0x11, 0x9a);
-
-	dsi_generic_write_seq(dsi, R69328_GAMMA_SET_A, 0x00,
-			      0x1a, 0x20, 0x28, 0x25, 0x24,
-			      0x26, 0x15, 0x13, 0x11, 0x18,
-			      0x1e, 0x1c, 0x00, 0x00, 0x1a,
-			      0x20, 0x28, 0x25, 0x24, 0x26,
-			      0x15, 0x13, 0x11, 0x18, 0x1e,
-			      0x1c, 0x00);
-	dsi_generic_write_seq(dsi, R69328_GAMMA_SET_B, 0x00,
-			      0x1a, 0x20, 0x28, 0x25, 0x24,
-			      0x26, 0x15, 0x13, 0x11, 0x18,
-			      0x1e, 0x1c, 0x00, 0x00, 0x1a,
-			      0x20, 0x28, 0x25, 0x24, 0x26,
-			      0x15, 0x13, 0x11, 0x18, 0x1e,
-			      0x1c, 0x00);
-	dsi_generic_write_seq(dsi, R69328_GAMMA_SET_C, 0x00,
-			      0x1a, 0x20, 0x28, 0x25, 0x24,
-			      0x26, 0x15, 0x13, 0x11, 0x18,
-			      0x1e, 0x1c, 0x00, 0x00, 0x1a,
-			      0x20, 0x28, 0x25, 0x24, 0x26,
-			      0x15, 0x13, 0x11, 0x18, 0x1e,
-			      0x1c, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, R69328_MACP, 0x04);
+
+	mipi_dsi_dcs_write_seq(dsi, R69328_POWER_SET, 0x14,
+			       0x1d, 0x21, 0x67, 0x11, 0x9a);
+
+	mipi_dsi_dcs_write_seq(dsi, R69328_GAMMA_SET_A, 0x00,
+			       0x1a, 0x20, 0x28, 0x25, 0x24,
+			       0x26, 0x15, 0x13, 0x11, 0x18,
+			       0x1e, 0x1c, 0x00, 0x00, 0x1a,
+			       0x20, 0x28, 0x25, 0x24, 0x26,
+			       0x15, 0x13, 0x11, 0x18, 0x1e,
+			       0x1c, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, R69328_GAMMA_SET_B, 0x00,
+			       0x1a, 0x20, 0x28, 0x25, 0x24,
+			       0x26, 0x15, 0x13, 0x11, 0x18,
+			       0x1e, 0x1c, 0x00, 0x00, 0x1a,
+			       0x20, 0x28, 0x25, 0x24, 0x26,
+			       0x15, 0x13, 0x11, 0x18, 0x1e,
+			       0x1c, 0x00);
+	mipi_dsi_dcs_write_seq(dsi, R69328_GAMMA_SET_C, 0x00,
+			       0x1a, 0x20, 0x28, 0x25, 0x24,
+			       0x26, 0x15, 0x13, 0x11, 0x18,
+			       0x1e, 0x1c, 0x00, 0x00, 0x1a,
+			       0x20, 0x28, 0x25, 0x24, 0x26,
+			       0x15, 0x13, 0x11, 0x18, 0x1e,
+			       0x1c, 0x00);
 
 	/* MACP On */
-	dsi_generic_write_seq(dsi, R69328_MACP, 0x03);
+	mipi_dsi_dcs_write_seq(dsi, R69328_MACP, 0x03);
 
 	ret = mipi_dsi_dcs_set_display_on(dsi);
 	if (ret < 0) {
diff --git a/include/dt-bindings/clock/mt8366-clk.h b/include/dt-bindings/clock/mt8366-clk.h
new file mode 100644
index 00000000000..9bf37db5cff
--- /dev/null
+++ b/include/dt-bindings/clock/mt8366-clk.h
@@ -0,0 +1,473 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)  */
+/*
+ * Copyright (c) 2026 MediaTek Inc.
+ * Author: Irving-CH Lin <irving-ch.lin@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8366_H
+#define _DT_BINDINGS_CLK_MT8366_H
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL				0
+#define CLK_APMIXED_ARMPLL_BL				1
+#define CLK_APMIXED_CCIPLL				2
+#define CLK_APMIXED_APLL1				3
+#define CLK_APMIXED_APLL2				4
+#define CLK_APMIXED_APLL3				5
+#define CLK_APMIXED_APLL4				6
+#define CLK_APMIXED_APLL5				7
+#define CLK_APMIXED_MAINPLL				8
+#define CLK_APMIXED_UNIVPLL				9
+#define CLK_APMIXED_MMPLL				10
+#define CLK_APMIXED_TVDPLL1				11
+#define CLK_APMIXED_TVDPLL2				12
+#define CLK_APMIXED_MSDCPLL				13
+#define CLK_APMIXED_MFGPLL				14
+#define CLK_APMIXED_APUPLL2				15
+#define CLK_APMIXED_APUPLL				16
+#define CLK_APMIXED_ETHPLL				17
+#define CLK_APMIXED_CANPLL				18
+#define CLK_APMIXED_EMIPLL				19
+
+/* TOPCKGEN */
+#define CLK_TOP_AXI_SEL					0
+#define CLK_TOP_SPM_SEL					1
+#define CLK_TOP_BUS_AXIMEM_SEL				2
+#define CLK_TOP_DISP_SEL				3
+#define CLK_TOP_EPD_SEL					4
+#define CLK_TOP_MDP_SEL					5
+#define CLK_TOP_DP_SEL					6
+#define CLK_TOP_IMG1_SEL				7
+#define CLK_TOP_IPE_SEL					8
+#define CLK_TOP_CAM_SEL					9
+#define CLK_TOP_CAMTM_SEL				10
+#define CLK_TOP_CAMTG_SEL				11
+#define CLK_TOP_CAMTG2_SEL				12
+#define CLK_TOP_MFG_REF_SEL				13
+#define CLK_TOP_UART_SEL				14
+#define CLK_TOP_SPI0_SEL				15
+#define CLK_TOP_SPI1_SEL				16
+#define CLK_TOP_SPI2_SEL				17
+#define CLK_TOP_SPI3_SEL				18
+#define CLK_TOP_SPI4_SEL				19
+#define CLK_TOP_SPI5_SEL				20
+#define CLK_TOP_I2CP_SEL				21
+#define CLK_TOP_I2C_SEL					22
+#define CLK_TOP_SENINF_SEL				23
+#define CLK_TOP_SENINF1_SEL				24
+#define CLK_TOP_VENC_SEL				25
+#define CLK_TOP_VDEC_SEL				26
+#define CLK_TOP_PWM_SEL					27
+#define CLK_TOP_DVFSRC_SEL				28
+#define CLK_TOP_AES_MSDCFBE_SEL				29
+#define CLK_TOP_MSDC_MACRO_0P_SEL			30
+#define CLK_TOP_MSDC_MACRO_1P_SEL			31
+#define CLK_TOP_MSDC_MACRO_2P_SEL			32
+#define CLK_TOP_MSDC50_0_SEL				33
+#define CLK_TOP_MSDC30_1_SEL				34
+#define CLK_TOP_MSDC30_2_SEL				35
+#define CLK_TOP_MSDC50_0_HCLK_SEL			36
+#define CLK_TOP_MSDC30_1_HCLK_SEL			37
+#define CLK_TOP_MSDC30_2_HCLK_SEL			38
+#define CLK_TOP_MCUPM_SEL				39
+#define CLK_TOP_DSI_OCC_SEL				40
+#define CLK_TOP_KP_IRQ_GEN_SEL				41
+#define CLK_TOP_NFI_BCLK_SEL				42
+#define CLK_TOP_SFLASH_SEL				43
+#define CLK_TOP_EMI_SEL					44
+#define CLK_TOP_MAC_TL_SEL				45
+#define CLK_TOP_SNPS_ETH_250M_SEL			46
+#define CLK_TOP_SNPS_ETH_62P4M_PTP_SEL			47
+#define CLK_TOP_SNPS_ETH_50M_RMII_SEL			48
+#define CLK_TOP_LVDSTX_CLKDIG_CTS_SEL			49
+#define CLK_TOP_VPLL_DPIX_SEL				50
+#define CLK_TOP_EPD_DPI_SEL				51
+#define CLK_TOP_DSP_SEL					52
+#define CLK_TOP_ECC_SEL					53
+#define CLK_TOP_GCPU_SEL				54
+#define CLK_TOP_USB_TOP_P0_SEL				55
+#define CLK_TOP_USB_XHCI_P0_SEL				56
+#define CLK_TOP_USB_TOP_P1_SEL				57
+#define CLK_TOP_USB_XHCI_P1_SEL				58
+#define CLK_TOP_USB_TOP_P2_SEL				59
+#define CLK_TOP_USB_XHCI_P2_SEL				60
+#define CLK_TOP_AUD_INTBUS_SEL				61
+#define CLK_TOP_AUD_ENGEN1_SEL				62
+#define CLK_TOP_AUD_ENGEN2_SEL				63
+#define CLK_TOP_EARC_ENGEN_SEL				64
+#define CLK_TOP_SPDIFIN_ENGEN_SEL			65
+#define CLK_TOP_LINEIN_ENGEN_SEL			66
+#define CLK_TOP_AUDIO_H_SEL				67
+#define CLK_TOP_VADSP_VOWPLL_SEL			68
+#define CLK_TOP_PWRAP_ULPOSC_SEL			69
+#define CLK_TOP_AUD_1_SEL				70
+#define CLK_TOP_AUD_2_SEL				71
+#define CLK_TOP_VADSP_26M_SEL				72
+#define CLK_TOP_ATB_SEL					73
+#define CLK_TOP_ASM_H_SEL				74
+#define CLK_TOP_I2SI4_M_SEL				75
+#define CLK_TOP_I2SI6_M_SEL				76
+#define CLK_TOP_I2SO4_M_SEL				77
+#define CLK_TOP_I2SO5_M_SEL				78
+#define CLK_TOP_I2SO6_M_SEL				79
+#define CLK_TOP_AUD_IEC_SEL				80
+#define CLK_TOP_SPDIFIN_SEL				81
+#define CLK_TOP_CAN0_SEL				82
+#define CLK_TOP_DISP_PWM_SEL				83
+#define CLK_TOP_SSPM_SEL				84
+#define CLK_TOP_VADSP_SEL				85
+#define CLK_TOP_APLL_TDMOUT_MCK_SEL			86
+#define CLK_TOP_MFG_SEL_MFGPLL				87
+#define CLK_TOP_APLL12_CK_DIV_I2SIN5			88
+#define CLK_TOP_APLL12_CK_DIV_I2SIN6			89
+#define CLK_TOP_APLL12_CK_DIV_I2SOUT4			90
+#define CLK_TOP_APLL12_CK_DIV_I2SOUT5			91
+#define CLK_TOP_APLL12_CK_DIV_I2SOUT6			92
+#define CLK_TOP_APLL12_CK_DIV_SPDIFOUT			93
+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M			94
+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B			95
+#define CLK_TOP_MAINPLL_D4				96
+#define CLK_TOP_MAINPLL_D4_D2				97
+#define CLK_TOP_MAINPLL_D4_D4				98
+#define CLK_TOP_MAINPLL_D4_D8				99
+#define CLK_TOP_MAINPLL_D5				100
+#define CLK_TOP_MAINPLL_D5_D2				101
+#define CLK_TOP_MAINPLL_D6				102
+#define CLK_TOP_MAINPLL_D6_D2				103
+#define CLK_TOP_MAINPLL_D6_D4				104
+#define CLK_TOP_MAINPLL_D7_D2				105
+#define CLK_TOP_MAINPLL_D7_D4				106
+#define CLK_TOP_MAINPLL_D7_D8				107
+#define CLK_TOP_MAINPLL_D9				108
+#define CLK_TOP_UNIVPLL_D4				109
+#define CLK_TOP_UNIVPLL_D4_D2				110
+#define CLK_TOP_UNIVPLL_D4_D4				111
+#define CLK_TOP_UNIVPLL_D4_D8				112
+#define CLK_TOP_UNIVPLL_D5				113
+#define CLK_TOP_UNIVPLL_D5_D2				114
+#define CLK_TOP_UNIVPLL_D5_D4				115
+#define CLK_TOP_UNIVPLL_D5_D8				116
+#define CLK_TOP_UNIVPLL_D6				117
+#define CLK_TOP_UNIVPLL_D6_D2				118
+#define CLK_TOP_UNIVPLL_D6_D4				119
+#define CLK_TOP_UNIVPLL_D6_D8				120
+#define CLK_TOP_UNIVPLL_D6_D16				121
+#define CLK_TOP_UNIVPLL_D7				122
+#define CLK_TOP_UNIVPLL_D7_D2				123
+#define CLK_TOP_UNIVPLL_D7_D3				124
+#define CLK_TOP_UNIVPLL_192M_D2				125
+#define CLK_TOP_UNIVPLL_192M_D4				126
+#define CLK_TOP_UNIVPLL_192M_D8				127
+#define CLK_TOP_UNIVPLL_192M_D16			128
+#define CLK_TOP_UNIVPLL_192M_D32			129
+#define CLK_TOP_UNIVPLL_192M_D10			130
+#define CLK_TOP_APLL1_D4				131
+#define CLK_TOP_APLL1_D3				132
+#define CLK_TOP_APLL2_D4				133
+#define CLK_TOP_APLL2_D3				134
+#define CLK_TOP_APLL3_D4				135
+#define CLK_TOP_APLL4_D4				136
+#define CLK_TOP_APLL5_D4				137
+#define CLK_TOP_MMPLL_D4				138
+#define CLK_TOP_MMPLL_D4_D2				139
+#define CLK_TOP_MMPLL_D4_D4				140
+#define CLK_TOP_MMPLL_D5				141
+#define CLK_TOP_MMPLL_D5_D2				142
+#define CLK_TOP_MMPLL_D6				143
+#define CLK_TOP_MMPLL_D6_D2				144
+#define CLK_TOP_MMPLL_D7				145
+#define CLK_TOP_TVDPLL1_D2				146
+#define CLK_TOP_TVDPLL1_D4				147
+#define CLK_TOP_TVDPLL1_D8				148
+#define CLK_TOP_TVDPLL1_D16				149
+#define CLK_TOP_TVDPLL2_D4				150
+#define CLK_TOP_TVDPLL2_D8				151
+#define CLK_TOP_MSDCPLL_D2				152
+#define CLK_TOP_ETHPLL_D2				153
+#define CLK_TOP_ETHPLL_D8				154
+#define CLK_TOP_ETHPLL_D10				155
+#define CLK_TOP_CANPLL_D5				156
+#define CLK_TOP_CANPLL_D10				157
+#define CLK_TOP_CANPLL_D20				158
+#define CLK_TOP_CANPLL_D25				159
+#define CLK_TOP_OSC_D2					160
+#define CLK_TOP_OSC_D4					161
+#define CLK_TOP_OSC_D8					162
+#define CLK_TOP_OSC_D16					163
+#define CLK_TOP_OSC_D10					164
+#define CLK_TOP_OSC_D20					165
+#define CLK_TOP_APLL12_DIV_I2SIN0_PDN			166
+#define CLK_TOP_APLL12_DIV_I2SIN1_PDN			167
+#define CLK_TOP_APLL12_DIV_I2SIN2_PDN			168
+#define CLK_TOP_APLL12_DIV_I2SIN3_PDN			169
+#define CLK_TOP_APLL12_DIV_I2SIN4_PDN			170
+#define CLK_TOP_APLL12_DIV_I2SIN6_PDN			171
+#define CLK_TOP_APLL12_DIV_I2SOUT0_PDN			172
+#define CLK_TOP_APLL12_DIV_I2SOUT1_PDN			173
+#define CLK_TOP_APLL12_DIV_I2SOUT2_PDN			174
+#define CLK_TOP_APLL12_DIV_I2SOUT3_PDN			175
+#define CLK_TOP_APLL12_DIV_I2SOUT4_PDN			176
+#define CLK_TOP_APLL12_DIV_I2SOUT5_PDN			177
+#define CLK_TOP_APLL12_DIV_I2SOUT6_PDN			178
+#define CLK_TOP_APLL12_DIV_SPDIFOUT_PDN			179
+#define CLK_TOP_APLL12_DIV_TDMOUT_M_PDN			180
+#define CLK_TOP_APLL12_DIV_TDMOUT_B_PDN			181
+#define CLK_TOP_F26M_CK_EN				182
+#define CLK_TOP_USB_F26M_CK_EN				183
+#define CLK_TOP_USB2_PHY_REFCK_P0_EN			184
+#define CLK_TOP_USB2_PHY_REFCK_P1_EN			185
+#define CLK_TOP_USB2_PHY_REFCK_P2_EN			186
+#define CLK_TOP_USB2_26M_CK_P0_EN			187
+#define CLK_TOP_USB2_26M_CK_P1_EN			188
+#define CLK_TOP_USB2_26M_CK_P2_EN			189
+#define CLK_TOP_FMCNT_P0_EN				190
+#define CLK_TOP_FMCNT_P1_EN				191
+#define CLK_TOP_FMCNT_P2_EN				192
+
+/* INFRACFG_AO_REG */
+#define CLK_INFRACFG_AO_REGP_UART0			0
+#define CLK_INFRACFG_AO_REGP_UART1			1
+#define CLK_INFRACFG_AO_REGP_UART2			2
+#define CLK_INFRACFG_AO_REGP_UART3			3
+#define CLK_INFRACFG_AO_REGP_DISP_PWM0			4
+#define CLK_INFRACFG_AO_REGP_DISP_PWM1			5
+#define CLK_INFRACFG_AO_REGP_SPI0_B			6
+#define CLK_INFRACFG_AO_REGP_SPI1_B			7
+#define CLK_INFRACFG_AO_REGP_SPI2_B			8
+#define CLK_INFRACFG_AO_REGP_SPI3_B			9
+#define CLK_INFRACFG_AO_REGP_SPI4_B			10
+#define CLK_INFRACFG_AO_REGP_SPI5_B			11
+#define CLK_INFRACFG_AO_REGP_SPI0_H			12
+#define CLK_INFRACFG_AO_REGP_SPI1_H			13
+#define CLK_INFRACFG_AO_REGP_SPI2_H			14
+#define CLK_INFRACFG_AO_REGP_SPI3_H			15
+#define CLK_INFRACFG_AO_REGP_SPI4_H			16
+#define CLK_INFRACFG_AO_REGP_SPI5_H			17
+#define CLK_INFRACFG_AO_REGP_AXI			18
+#define CLK_INFRACFG_AO_REGP_AHB			19
+#define CLK_INFRACFG_AO_REGP_TL				20
+#define CLK_INFRACFG_AO_REGP_REF			21
+#define CLK_INFRACFG_AO_REGP_DMA_B			22
+#define CLK_INFRACFG_AO_REGP_SSUSB0_PIPE		23
+#define CLK_INFRACFG_AO_REGP_SSUSB0_REF			24
+#define CLK_INFRACFG_AO_REGP_SSUSB0_FRMCNT		25
+#define CLK_INFRACFG_AO_REGP_SSUSB0_UTMI		26
+#define CLK_INFRACFG_AO_REGP_SSUSB0_SYS			27
+#define CLK_INFRACFG_AO_REGP_SSUSB0_XCHI		28
+#define CLK_INFRACFG_AO_REGP_SSUSB0_F			29
+#define CLK_INFRACFG_AO_REGP_SSUSB0_H			30
+#define CLK_INFRACFG_AO_REGP_SSUSB1_REF			31
+#define CLK_INFRACFG_AO_REGP_SSUSB1_FRMCNT		32
+#define CLK_INFRACFG_AO_REGP_SSUSB1_UTMI		33
+#define CLK_INFRACFG_AO_REGP_SSUSB1_SYS			34
+#define CLK_INFRACFG_AO_REGP_SSUSB1_XCHI		35
+#define CLK_INFRACFG_AO_REGP_SSUSB1_F			36
+#define CLK_INFRACFG_AO_REGP_SSUSB1_H			37
+#define CLK_INFRACFG_AO_REGP_SSUSB2_REF			38
+#define CLK_INFRACFG_AO_REGP_SSUSB2_FRMCNT		39
+#define CLK_INFRACFG_AO_REGP_SSUSB2_UTMI		40
+#define CLK_INFRACFG_AO_REGP_SSUSB2_SYS			41
+#define CLK_INFRACFG_AO_REGP_SSUSB2_XCHI		42
+#define CLK_INFRACFG_AO_REGP_SSUSB2_F			43
+#define CLK_INFRACFG_AO_REGP_SSUSB2_H			44
+#define CLK_INFRACFG_AO_REG_PMIC_TMR			45
+#define CLK_INFRACFG_AO_REG_PMIC_AP			46
+#define CLK_INFRACFG_AO_REG_SEJ				47
+#define CLK_INFRACFG_AO_REG_MCUPM			48
+#define CLK_INFRACFG_AO_REG_GCE				49
+#define CLK_INFRACFG_AO_REG_GCE2			50
+#define CLK_INFRACFG_AO_REG_PWM_H			51
+#define CLK_INFRACFG_AO_REG_PWM1			52
+#define CLK_INFRACFG_AO_REG_PWM2			53
+#define CLK_INFRACFG_AO_REG_PWM3			54
+#define CLK_INFRACFG_AO_REG_PWM4			55
+#define CLK_INFRACFG_AO_REG_PWM				56
+#define CLK_INFRACFG_AO_REG_GCE_26M			57
+#define CLK_INFRACFG_AO_REG_CQ_DMA_FPC			58
+#define CLK_INFRACFG_AO_REG_BTIF			59
+#define CLK_INFRACFG_AO_REG_SPI0			60
+#define CLK_INFRACFG_AO_REG_AUXADC			61
+#define CLK_INFRACFG_AO_REG_CPUM			62
+#define CLK_INFRACFG_AO_REG_CCIF1_AP			63
+#define CLK_INFRACFG_AO_REG_CCIF1_MD			64
+#define CLK_INFRACFG_AO_REG_AUXADC_MD			65
+#define CLK_INFRACFG_AO_REG_TL_26M			66
+#define CLK_INFRACFG_AO_REG_TL_96M			67
+#define CLK_INFRACFG_AO_REG_PL_P_250M			68
+#define CLK_INFRACFG_AO_REG_CCIF_AP			69
+#define CLK_INFRACFG_AO_REG_DEBUGSYS			70
+#define CLK_INFRACFG_AO_REG_AUDIO			71
+#define CLK_INFRACFG_AO_REG_CCIF_MD			72
+#define CLK_INFRACFG_AO_REG_DBG_TRACE			73
+#define CLK_INFRACFG_AO_REG_CLDMA_BCLK			74
+#define CLK_INFRACFG_AO_REG_AUDIO_26M_BCLK		75
+#define CLK_INFRACFG_AO_REG_MODEM_TEMP_SHARE		76
+#define CLK_INFRACFG_AO_REG_SPI1			77
+#define CLK_INFRACFG_AO_REG_SPI2			78
+#define CLK_INFRACFG_AO_REG_SPI3			79
+#define CLK_INFRACFG_AO_REG_U_SAP_B			80
+#define CLK_INFRACFG_AO_REG_UNIPRO_MBIST		81
+#define CLK_INFRACFG_AO_REG_SPI4			82
+#define CLK_INFRACFG_AO_REG_SPI5			83
+#define CLK_INFRACFG_AO_REG_CQ_DMA			84
+#define CLK_INFRACFG_AO_REG_KP_IRQ_GEN			85
+#define CLK_INFRACFG_AO_REG_KP_32K			86
+#define CLK_INFRACFG_AO_REG_U_AXI			87
+#define CLK_INFRACFG_AO_REG_CCIF5_AP			88
+#define CLK_INFRACFG_AO_REG_CCIF5_MD			89
+#define CLK_INFRACFG_AO_REG_CCIF2_AP			90
+#define CLK_INFRACFG_AO_REG_CCIF2_MD			91
+#define CLK_INFRACFG_AO_REG_CCIF3_AP			92
+#define CLK_INFRACFG_AO_REG_CCIF3_MD			93
+#define CLK_INFRACFG_AO_REG_SEJ_F13M			94
+#define CLK_INFRACFG_AO_REG_AES				95
+#define CLK_INFRACFG_AO_REG_GCPU			96
+#define CLK_INFRACFG_AO_REG_ECC				97
+#define CLK_INFRACFG_AO_REG_CCIF4_AP			98
+#define CLK_INFRACFG_AO_REG_CCIF4_MD			99
+#define CLK_INFRACFG_AO_REGP_AUXADC_26M			100
+#define CLK_INFRACFG_AO_REGP_MSDC0			101
+#define CLK_INFRACFG_AO_REGP_MSDC0_H			102
+#define CLK_INFRACFG_AO_REGP_MSDC0_FAES			103
+#define CLK_INFRACFG_AO_REGP_MSDC0_MST_F		104
+#define CLK_INFRACFG_AO_REGP_MSDC0_SLV_H		105
+#define CLK_INFRACFG_AO_REGP_MSDC1			106
+#define CLK_INFRACFG_AO_REGP_MSDC1_H			107
+#define CLK_INFRACFG_AO_REGP_MSDC1_MST_F		108
+#define CLK_INFRACFG_AO_REGP_MSDC1_SLV_H		109
+#define CLK_INFRACFG_AO_REGP_MSDC2			110
+#define CLK_INFRACFG_AO_REGP_MSDC2_H			111
+#define CLK_INFRACFG_AO_REGP_MSDC2_MST_F		112
+#define CLK_INFRACFG_AO_REGP_MSDC2_SLV_H		113
+#define CLK_INFRACFG_AO_REGP_SFLASH			114
+#define CLK_INFRACFG_AO_REGP_SFLASH_F			115
+#define CLK_INFRACFG_AO_REGP_SFLASH_H			116
+#define CLK_INFRACFG_AO_REGP_SFLASH_P			117
+#define CLK_INFRACFG_AO_REGP_BTIF_B			118
+#define CLK_INFRACFG_AO_REGP_CAN0_P			119
+#define CLK_INFRACFG_AO_REGP_CAN0			120
+#define CLK_INFRACFG_AO_REGP_NFI_H			121
+#define CLK_INFRACFG_AO_REGP_NFI_B			122
+#define CLK_INFRACFG_AO_REGP_NFIECC_B			123
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMPC_I2C1					0
+#define CLK_IMPC_I2C2					1
+#define CLK_IMPC_I2C3					2
+#define CLK_IMPC_I2C5					3
+#define CLK_IMPC_I2C6					4
+#define CLK_IMPC_I2C7					5
+#define CLK_IMPC_I2C8					6
+#define CLK_IMPC_I2C9					7
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_I2C0					0
+#define CLK_IMPE_I2C4					1
+
+/* DISPSYS_CONFIG */
+#define CLK_MM_DISP_OVL0_4L				0
+#define CLK_MM_DISP_OVL1_4L				1
+#define CLK_MM_DISP_RSZ0				2
+#define CLK_MM_DISP_RSZ1				3
+#define CLK_MM_DISP_RDMA0				4
+#define CLK_MM_DISP_RDMA1				5
+#define CLK_MM_DISP_COLOR1				6
+#define CLK_MM_DISP_CCORR1				7
+#define CLK_MM_DISP_CCORR3				8
+#define CLK_MM_DISP_AAL1				9
+#define CLK_MM_DISP_GAMMA1				10
+#define CLK_MM_DISP_DITHER1				11
+#define CLK_MM_VPP_MERGE0				12
+#define CLK_MM_DISP_DSI0_MM				13
+#define CLK_MM_DP_INTF0_MM				14
+#define CLK_MM_DPI0_MM					15
+#define CLK_MM_DISP_WDMA0				16
+#define CLK_MM_DISP_DSI1_MM				17
+#define CLK_MM_DISP_FAKE_ENG0				18
+#define CLK_MM_DISP_FAKE_ENG1				19
+#define CLK_MM_SMI_SUB_COMMON				20
+#define CLK_MM_DISP_MUTEX0				21
+#define CLK_MM_DISP_APB_BUS				22
+#define CLK_MM_LVDS_ENCODER				23
+#define CLK_MM_EPD_DLI_ASYNC				24
+#define CLK_MM_SMI					25
+#define CLK_MM_DISP_DSI0				26
+#define CLK_MM_DPI0					27
+#define CLK_MM_LVDS_ENCODER_PXL				28
+#define CLK_MM_DISP_DSI1				29
+#define CLK_MM_DP_INTF0					30
+#define CLK_MM_LVDS_ENCODER_CTS				31
+#define CLK_MM_AXI					32
+#define CLK_MM_EPDSYS					33
+#define CLK_MM_MM_CK_GLOBAL				34
+#define CLK_MM_DISP_DSI0_CK_GLOBAL			35
+#define CLK_MM_LVDS_PXL_CK_GLOBAL			36
+#define CLK_MM_DISP_DSI1_GLOBAL				37
+#define CLK_MM_DP_CK_GLOBAL				38
+#define CLK_MM_LVDS_CTS_CK_GLOBAL			39
+#define CLK_MM_AXI_CK_GLOBAL				40
+#define CLK_MM_EPDSYS_CK_GLOBAL				41
+#define CLK_MM_26M					42
+#define CLK_MM_32K					43
+
+/* DPTX_PHYD_SIFSLV_DIG_GLB */
+#define CLK_DPTX_PHYD_SIFSLV_DIG_GLB_RG_REF_CK_ENA	0
+
+/* EPDSYS_CONFIG */
+#define CLK_EPDSYS_PIPELINE_TOP				0
+#define CLK_EPDSYS_PIPELINE_IMAGE_RDMA			1
+#define CLK_EPDSYS_PIPELINE_WORKING_RDMA		2
+#define CLK_EPDSYS_PIPELINE_WDMA			3
+#define CLK_EPDSYS_PIPELINE_WF_LUT_TOP			4
+#define CLK_EPDSYS_PIPELINE_DPI				5
+#define CLK_EPDSYS_PIPELINE_6				6
+#define CLK_EPDSYS_PIPELINE_IMAGE_PROCESS		7
+#define CLK_EPDSYS_DISP_COLOR				8
+#define CLK_EPDSYS_DISP_CCORR				9
+#define CLK_EPDSYS_DPI					10
+#define CLK_EPDSYS_TCON					11
+#define CLK_EPDSYS_SMI_LARB3				12
+#define CLK_EPDSYS_SMI_LARB8				13
+#define CLK_EPDSYS_IMG_DL_RELAY				14
+#define CLK_EPDSYS_26M_HRTWT				15
+#define CLK_EPDSYS_DPI0_MM				16
+
+/* VDEC_GCON_BASE */
+#define CLK_VDE2_LARB1_CKEN				0
+#define CLK_VDE2_LAT_CKEN				1
+#define CLK_VDE2_LAT_ACTIVE				2
+#define CLK_VDE2_LAT_CKEN_ENG				3
+#define CLK_VDE2_MINI_MDP_EN				4
+#define CLK_VDE2_VDEC_CKEN				5
+#define CLK_VDE2_VDEC_ACTIVE				6
+#define CLK_VDE2_VDEC_CKEN_ENG				7
+
+/* IPE */
+#define CLK_IPE_LARB19					0
+#define CLK_IPE_LARB20					1
+#define CLK_IPE_SMI_SUBCOM				2
+#define CLK_IPE_FD					3
+#define CLK_IPE_FE					4
+#define CLK_IPE_RSC					5
+#define CLK_IPE_GALS					6
+
+/* CAMSYS_MAIN */
+#define CLK_CAM_M_LARB13				0
+#define CLK_CAM_M_DFP_VAD				1
+#define CLK_CAM_M_LARB14				2
+#define CLK_CAM_M_CAM					3
+#define CLK_CAM_M_CAMTG					4
+#define CLK_CAM_M_SENINF				5
+#define CLK_CAM_M_CAMSV1				6
+#define CLK_CAM_M_CAMSV2				7
+#define CLK_CAM_M_CAMSV3				8
+#define CLK_CAM_M_CCU0					9
+#define CLK_CAM_M_CCU1					10
+#define CLK_CAM_M_MRAW0					11
+#define CLK_CAM_M_FAKE_ENG				12
+#define CLK_CAM_M_CCU_GALS				13
+#define CLK_CAM_M_CAM2MM_GALS				14
+#define CLK_CAM_M_CAMSV4				15
+#define CLK_CAM_M_PDA					16
+
+#endif /* _DT_BINDINGS_CLK_MT8366_H */
diff --git a/include/dt-bindings/power/mediatek,mt8366-power.h b/include/dt-bindings/power/mediatek,mt8366-power.h
new file mode 100644
index 00000000000..a09bcd01d05
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8366-power.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (c) 2026 MediaTek Inc.
+ * Author: Irving-ch Lin <irving-ch.lin@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8366_POWER_H
+#define _DT_BINDINGS_POWER_MT8366_POWER_H
+
+/* SPM */
+#define MT8366_POWER_DOMAIN_CONN			0
+#define MT8366_POWER_DOMAIN_MFG0			1
+#define MT8366_POWER_DOMAIN_MFG1			2
+#define MT8366_POWER_DOMAIN_MFG2			3
+#define MT8366_POWER_DOMAIN_MFG3			4
+#define MT8366_POWER_DOMAIN_VDEC			5
+#define MT8366_POWER_DOMAIN_VENC			6
+#define MT8366_POWER_DOMAIN_AUDIO			7
+#define MT8366_POWER_DOMAIN_CAM				8
+#define MT8366_POWER_DOMAIN_CAM_RAWA			9
+#define MT8366_POWER_DOMAIN_DISP			10
+#define MT8366_POWER_DOMAIN_DP_TX			11
+#define MT8366_POWER_DOMAIN_PCIE			12
+#define MT8366_POWER_DOMAIN_ISP_IMG1			13
+#define MT8366_POWER_DOMAIN_ISP_IMG2			14
+#define MT8366_POWER_DOMAIN_ISP_IPE			15
+#define MT8366_POWER_DOMAIN_MMLSYS_SHUTDOWN		16
+#define MT8366_POWER_DOMAIN_EPD				17
+#define MT8366_POWER_DOMAIN_CSI_RX			18
+#define MT8366_POWER_DOMAIN_VADSP_AO			19
+#define MT8366_POWER_DOMAIN_VADSP_INFRA			20
+
+#endif /* _DT_BINDINGS_POWER_MT8366_POWER_H */
diff --git a/include/mipi_dsi.h b/include/mipi_dsi.h
index 4ca05f71e29..69ee8d49812 100644
--- a/include/mipi_dsi.h
+++ b/include/mipi_dsi.h
@@ -267,6 +267,24 @@ int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
 
 ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
 			       size_t size);
+
+/**
+ * mipi_dsi_generic_write_seq - transmit data using a generic write packet
+ * @dsi: DSI peripheral device
+ * @cmd: Command
+ * @seq: buffer containing the payload
+ *
+ * This macro returns from the calling function with a negative error code on
+ * failure.
+ */
+#define mipi_dsi_generic_write_seq(dsi, cmd, seq...) do {		\
+		static const u8 b[] = { cmd, seq };			\
+		int ret;						\
+		ret = mipi_dsi_generic_write(dsi, b, ARRAY_SIZE(b));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
 ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params,
 			      size_t num_params, void *data, size_t size);
 
@@ -304,6 +322,23 @@ ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi,
 				  const void *data, size_t len);
 
 /**
+ * mipi_dsi_dcs_write_seq - transmit a DCS command with payload
+ * @dsi: DSI peripheral device
+ * @cmd: DCS command
+ * @seq: buffer containing the payload
+ *
+ * This macro returns from the calling function with a negative error code on
+ * failure.
+ */
+#define mipi_dsi_dcs_write_seq(dsi, cmd, seq...) do {			\
+		static const u8 b[] = { cmd, seq };			\
+		int ret;						\
+		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
+/**
  * mipi_dsi_dcs_write() - send DCS write command
  * @dsi: DSI peripheral device
  * @cmd: DCS command