net: stmmac: Add system interface data bus width property support

DW *MAC IP-cores can be synthesized with various system interface data bus
widths. For instance DW GMACs and DW QoS Ether can work with buses of 32,
64 and 128 bits width, while DW xGMACs can be created with system bus of
64 and 128 bits width. The bus width value affects several very important
parameters like DMA transfers granularity and performance, DMA maximum
burst length, Rx DMA buffers alignment. So in order to be able to tune and
verify these parameters let's add the data bus width device property
support. It can be passed either by the platform code or via the DT-node
property. For some reason HW capability register doesn't contain that
parameter in its fields.

Note if the data bus width isn't specified then the driver will use the
default value of 16 bytes. That will apply the strongest constraint on the
PBL values and Rx DMA buffers alignment (the later one is actually
currently hard-coded anyway). In order to get a better HW performance it's
preferable to specify the actual value for a particular version of the
controller.

Signed-off-by: Serge Semin <fancer.lancer@gmail.com>

3 files changed, 15 insertions, 0 deletions

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index a34aebb775b4..7cacc3aa6b39 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -7943,6 +7943,14 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
 		dev_info(priv->device, "No HW DMA feature register supported\n");
 	}
 
+	/* Set the data bus width of the system interface to 16 bytes by
+	 * default. It will apply the strongest constraint on the Tx FIFO size
+	 * and the Rx DMA buffers alignment, but at least we'll be on a safe
+	 * side from possible HW UBs.
+	 */
+	if (!priv->plat->data_width)
+		priv->plat->data_width = 16;
+
 	if (priv->plat->rx_coe)
 		dev_info(priv->device, "RX Checksum Offload Engine supported\n");
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 617fedff7ef9..03f1498eca3b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -496,6 +496,12 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)
 
 	of_property_read_u32(np, "rx-fifo-depth", &plat->rx_fifo_size);
 
+	/* Default to 16 bytes data bus width to be on a safe side at the
+	 * PBL upper limit and the Rx DMA buffer alignment calculation.
+	 */
+	if (of_property_read_u32(np, "snps,data-width", &plat->data_width))
+		plat->data_width = 16;
+
 	plat->force_sf_dma_mode =
 		of_property_read_bool(np, "snps,force_sf_dma_mode");
 
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 934a536a3a0f..d9c9ef8a933f 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -241,6 +241,7 @@ struct plat_stmmacenet_data {
 	int unicast_filter_entries;
 	int tx_fifo_size;
 	int rx_fifo_size;
+	u32 data_width;
 	u32 host_dma_width;
 	u32 rx_queues_to_use;
 	u32 tx_queues_to_use;