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authorSerge Semin <fancer.lancer@gmail.com>2025-08-20 01:17:22 +0300
committerSerge Semin <fancer.lancer@gmail.com>2026-08-13 20:26:33 +0300
commite21aefd28685730a6a09fe38635ef6fade3fd4d0 (patch)
tree7c9f1856d6fbe072f8444482f4a7998d70eb8f1a
parent2961718acc14ac70f51ea7ecfa4851b04e317500 (diff)
downloadlinux-e21aefd28685730a6a09fe38635ef6fade3fd4d0.tar.gz
linux-e21aefd28685730a6a09fe38635ef6fade3fd4d0.zip
net: stmmac: Collect DMA missing frames stats non-mutually
Every DW MAC IP-core has a register called like "Missed Frame and Buffer Overflow Counter". It exposes two counters being incremented on each frame dropped due to FIFO overflow or DMA Rx-descriptor unavailable (Rx MTL FIFO flushing). They exist irrespective from the MMC module availability. Moreover expose the statistics unavailable in the MAC Management Counters. So let's convert the code collecting MAC Management/Debug and DMA-missing frames statistics to being linear and not mutually exclusive. Also note currently the DMA missing frames stats is collected for the old DW MAC IP-core. This change is also a preparation before adding the counters support for the rest of the DW controllers. Fixes: 1c901a46d576 ("stmmac: add MMC support exported via ethtool (v3)") Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c43
1 files changed, 21 insertions, 22 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index 9881b8df1e64..b3ad74fe8f69 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -537,10 +537,11 @@ static void stmmac_get_ethtool_stats(struct net_device *dev,
u32 rx_queues_count = priv->plat->rx_queues_to_use;
u32 tx_queues_count = priv->plat->tx_queues_to_use;
u64 napi_poll = 0, normal_irq_n = 0;
- int i, j = 0, pos, ret;
unsigned long count;
unsigned int start;
+ int i, j = 0, pos;
+ /* Update the statistics by reading from the HW counters */
if (priv->dma_cap.asp) {
for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
@@ -549,32 +550,30 @@ static void stmmac_get_ethtool_stats(struct net_device *dev,
}
}
- /* Update the DMA HW counters for dwmac10/100 */
- ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr);
- if (ret) {
- /* If supported, for new GMAC chips expose the MMC counters */
- if (priv->dma_cap.rmon) {
- stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
+ if (priv->dma_cap.rmon) {
+ stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
- for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
- char *p;
- p = (char *)priv + stmmac_mmc[i].stat_offset;
+ for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
+ char *p;
+ p = (char *)priv + stmmac_mmc[i].stat_offset;
- data[j++] = (stmmac_mmc[i].sizeof_stat ==
- sizeof(u64)) ? (*(u64 *)p) :
- (*(u32 *)p);
- }
- }
- if (priv->dma_cap.eee) {
- int val = phylink_get_eee_err(priv->phylink);
- if (val)
- priv->xstats.phy_eee_wakeup_error_n = val;
+ data[j++] = (stmmac_mmc[i].sizeof_stat == sizeof(u64)) ?
+ (*(u64 *)p) : (*(u32 *)p);
}
+ }
- stmmac_mac_debug(priv, priv->ioaddr,
- (void *)&priv->xstats,
- rx_queues_count, tx_queues_count);
+ if (priv->dma_cap.eee) {
+ int val = phylink_get_eee_err(priv->phylink);
+ if (val)
+ priv->xstats.phy_eee_wakeup_error_n = val;
}
+
+ stmmac_mac_debug(priv, priv->ioaddr,
+ (void *)&priv->xstats,
+ rx_queues_count, tx_queues_count);
+
+ stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr);
+
for (i = 0; i < STMMAC_STATS_LEN; i++) {
char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==