kernel/git/next/linux-next.git/drivers/clk/qcom, branch master

Merge branches 'arm64-defconfig-for-7.4', 'arm64-fixes-for-7.3', 'arm64-for-7.4', 'clk-fixes-for-7.3', 'clk-for-7.4', 'drivers-fixes-for-7.3' and 'drivers-for-7.4' into for-next

2026-09-11T03:14:34+00:00

clk: qcom: Add Global Clock Controller driver for Kuno

2026-08-31T22:37:49+00:00

Add the global clock controller (GCC) driver for the Qualcomm Kuno SoC, providing the PLLs, root clock generators, gate/branch clocks and resets used by the peripheral devices such as UART, SPI, I2C, USB, SD, PCIe and Ethernet. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma Link: https://lore.kernel.org/r/20260827-kuno-soc-support-v5-11-6d47636a8f09@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: clk-rpmh: Add support for Kuno RPMh clocks

2026-08-31T22:36:36+00:00

Add the RPMh clock description for the Qualcomm Kuno SoC so the qcom,kuno-rpmh-clk compatible can provide the RPMh-managed clocks to consumers: the CXO div-2 (and always-on variant), RF clock 1 (and always-on variant), the QPIC BCM clock and the IPA clock. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma Link: https://lore.kernel.org/r/20260827-kuno-soc-support-v5-5-6d47636a8f09@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: alpha-pll: Check Lucid Ole PLL status before configuring

2026-08-31T20:17:33+00:00

On some platforms such as SM8475, not doing this may result in graphical glitches when the mdss driver takes over. This fixes the aforementioned issue. Fixes: 3132a9a11e57 ("clk: qcom: clk-alpha-pll: Add support for lucid ole pll configure") Signed-off-by: Esteban Urrutia Reviewed-by: Konrad Dybcio Suggested-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260713-sm8450-qol-dispcc-v3-3-56fd05822270@proton.me Signed-off-by: Bjorn Andersson

clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data

2026-08-31T20:17:33+00:00

Migrate to qcom_cc_driver_data, which is used by other clock controller drivers. Reviewed-by: Konrad Dybcio Signed-off-by: Esteban Urrutia Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260713-sm8450-qol-dispcc-v3-2-56fd05822270@proton.me Signed-off-by: Bjorn Andersson

clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops

2026-08-31T20:17:33+00:00

If the clock frequency is changed at registration time, a flicker will be visible at boot. Switching to clk_rcg2_shared_no_init_park_ops fixes this. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") Reviewed-by: Konrad Dybcio Signed-off-by: Esteban Urrutia Link: https://lore.kernel.org/r/20260713-sm8450-qol-dispcc-v3-1-56fd05822270@proton.me Signed-off-by: Bjorn Andersson

clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled

2026-08-31T20:16:46+00:00

Allow Venus core GDSCs to have their control passed to hardware, so they can be powered on by Venus firmware and explicitly state that the vcodec clocks' halt bit should be checked. Signed-off-by: Erikas Bitovtas Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue [André: Update commit message] Signed-off-by: André Apitzsch Link: https://lore.kernel.org/r/20260731-msm8939-venus-rfc-v10-1-9ac503250fc7@apitzsch.eu Signed-off-by: Bjorn Andersson

clk: qcom: camcc: Add support for camera clock controller for Nord

2026-08-31T20:14:03+00:00

Add support for the Camera Clock Controller (CAMCC) on the Nord platform for camera SW drivers to request for these clocks. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-6-674d7718e41f@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: videocc-glymur: Add video clock controller support for Nord

2026-08-31T20:13:08+00:00

Nord shares the video clock controller topology with Glymur, differing only in the PLL0 hardware (Lucid-OLE vs Taycan-EKO-T) and the MVS0 frequency table. Extend the existing Glymur video clock controller driver to also probe on the qcom,nord-videocc compatible, switching to the Nord PLL configuration, VCO table, and MVS0 frequency table at probe time. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-5-674d7718e41f@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: nwgcc-nord: Add video axi clock resets for Nord

2026-08-31T20:12:39+00:00

The global clock controller video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-2-674d7718e41f@oss.qualcomm.com Signed-off-by: Bjorn Andersson