The linux-next integration testing tree https://git.landau.one/pub/scm/linux/kernel/git/next/linux-next.git/atom?h=master 2026-09-10T12:20:55+00:00 2026-09-10T12:20:55+00:00 Mark Brown broonie@kernel.org 2026-09-10T12:20:55+00:00 urn:sha1:0f6067db1a9c610bdccde6f34b1e096f9c962a1e 2026-09-10T12:20:53+00:00 Mark Brown broonie@kernel.org 2026-09-10T12:20:53+00:00 urn:sha1:9045ed496826db0acb06642f255841c2c85ddbf5 2026-09-10T12:20:38+00:00 Mark Brown broonie@kernel.org 2026-09-10T12:20:38+00:00 urn:sha1:49df50a1d5e00c33a43e4942b1ce046ae46472a0 2026-09-10T12:20:37+00:00 Mark Brown broonie@kernel.org 2026-09-10T12:20:37+00:00 urn:sha1:76dd5af064a56c277dd2ac77dd7345bdc27c38c5 2026-09-10T12:20:32+00:00 Mark Brown broonie@kernel.org 2026-09-10T12:20:32+00:00 urn:sha1:c9c2695849b82cd0b0c023e44322a196a955c77d 2026-09-09T08:49:36+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2026-08-17T19:25:34+00:00 urn:sha1:810b8b6c4e02c40991c29491cec09ebdaf5ec6d0 Register a syscon regmap for the System Controller (SYSC) integrated into the RZ/T2H and RZ/N2H CPG block. Unlike traditional Renesas CPG/MSSR implementations, the RZ/T2H and RZ/N2H CPG block also integrates the SYSC, which provides low-power management, clock monitoring, write protection and peripheral configuration registers shared by multiple drivers. Implement the RZ/T2H-specific .post_init() callback to create and register a syscon regmap covering the SYSC register space using the CPG device node. For backward compatibility, return without registering the regmap when the mapped resources correspond to older Device Trees that expose only the legacy 64 KiB CPG register window. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260817192540.423994-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2026-09-09T08:48:37+00:00 Geert Uytterhoeven geert+renesas@glider.be 2026-09-03T12:05:25+00:00 urn:sha1:91df590e41982844e5b0c2d100cf7339dbbad454 Improve readability by using the FIELD_GET() helper instead of open-coding the same operation, and by adding field definitions to get rid of hardcoded values. While at it, move register definitions that are only used inside the rcar-gen3-cpg.c source file out of the rcar-gen3-cpg.h header file. Add comments where appropriate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://patch.msgid.link/17c50847f86b814150573e34cc64913f09598f0f.1788437047.git.geert+renesas@glider.be 2026-09-08T20:14:10+00:00 Sudeep Holla sudeep.holla@kernel.org 2026-09-08T20:14:10+00:00 urn:sha1:b8e87c5923e1f6f6a11e20ab3c9671802f123f58 Arm firmware fixes for v7.3 SCPI fixes address resource leaks and invalid firmware responses, while FF-A gains shutdown cleanup needed for normal kexec. - Release the device node reference acquired during SCPI domain lookup. - Validate SCPI DVFS OPP counts and indices returned by firmware to prevent out-of-bounds accesses and invalid clock rates. - Register the SCPI cpufreq device only once across DVFS providers, preserving the registered device pointer for cleanup and allowing retries after registration failure. - Run FF-A teardown during orderly shutdown so notifications, partition devices and RX/TX mappings are released before a replacement kernel boots through normal kexec. Also includes replacing a literal platform device ID with PLATFORM_DEVID_NONE and correcting an SCMI comment typo. * tag 'scmi-ffa-fixes-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: firmware: arm_scmi: Fix typo "upto" in comment firmware: arm_ffa: Tear down driver during shutdown clk: scpi: use PLATFORM_DEVID_NONE for scpi-cpufreq clk: scpi: register scpi-cpufreq once and clear on failure clk: scpi: bound-check DVFS index in scpi_dvfs_recalc_rate firmware: arm_scpi: reject DVFS OPP count above MAX_DVFS_OPPS firmware: arm_scpi: fix device_node leak in scpi_dev_domain_id 2026-09-07T10:02:19+00:00 Aiden Isik aidenisik@member.fsf.org 2026-08-18T21:58:37+00:00 urn:sha1:0ae5dad7d9e6e4b8c8f3611f04fa929e634630e5 CMU_TOP is the top level clock management unit which contains PLLs, muxes, dividers and gates that feed the other clock management units. CMU_PERI provides clocks for USI blocks and their children, PWM, MCT, and watchdog timers. CMU_FSYS provides clocks for MMC, USB, GPIO, etc. More blocks will be added as device drivers which utilise them are added. Signed-off-by: Aiden Isik <aidenisik@member.fsf.org> Link: https://patch.msgid.link/20260818-for-next-lucky7-clock-v2-3-cda0cc80f158@member.fsf.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> 2026-09-07T10:02:18+00:00 Aiden Isik aidenisik@member.fsf.org 2026-08-18T21:58:36+00:00 urn:sha1:6fb3239a9a58399ea787887ad555b6f6cfadbddb pll_309 (referred to in the downstream kernel sources as frd_309_rpll) is one of two PLLs used in the Exynos5515 SoC. It is an integer/fractional PLL with an FVCO of 600-2400MHz. It has the same locktime (500), and kdiv/mdiv/pdiv/sdiv masks and shifts as pll_531x, so it can be handled in exactly the same way. When defining a PLL, the "con" parameter should be set to the CON3 register, like this: PLL(pll_309, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), Signed-off-by: Aiden Isik <aidenisik@member.fsf.org> Link: https://patch.msgid.link/20260818-for-next-lucky7-clock-v2-2-cda0cc80f158@member.fsf.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>