The linux-next integration testing tree https://git.landau.one/pub/scm/linux/kernel/git/next/linux-next.git/atom?h=master 2026-09-07T13:27:55+00:00 2026-09-07T13:27:55+00:00 Mark Brown broonie@kernel.org 2026-09-07T13:27:55+00:00 urn:sha1:806deb2951efd8f2762615e7e8db374ada3b76d7 2026-09-05T04:37:00+00:00 Kees Cook kees+treewide@kernel.org 2026-09-02T22:31:14+00:00 urn:sha1:3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook <kees+treewide@kernel.org> 2026-09-01T03:10:39+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-09-01T03:10:39+00:00 urn:sha1:786262be6048deab760f68c8acc2c85607165894 Pull forgotten EDAC updates from Borislav Petkov: "Somewhat belated (and forgotten :-\) EDAC updates lineup for v7.3: - Mark the mpc85xx and ThunderX EDAC drivers as orphaned due to lack of access to hardware - Remove the unused fake error injection interface from the EDAC debugfs code due to potential races between logging a fake and a real hw error - edac_mc_sysfs: Use sysfs_emit_at() for proper bounds checking - Remove Mark Gross from maintainer entries and move him to CREDITS - Load the AMD address translation library only on systems which can actually make use of it (have ECC memory) instead of on every AMD Zen system out there - In edac_altera, detect the SoC variant using the ECC manager's compatible string instead of the build architecture to select the correct interrupt layout, and remove leftover architecture-specific ifdeffery from the double-bit error handling path - Add a new reviewer for the Xilinx EDAC drivers - Unify address translation logic in Intel client EDAC drivers igen6 and ie31200 along with detecting memory controller counts at boot time instead of relying on hardcoded, platform specific numbers. Also, fix a bunch of issues in them; work by Qiuxu Zhuo - Add support for a new Intel processor platform Starfire which is a derivative of Panther Lake SoCs - The usual cleanups and fixlets all over" * tag 'edac_updates_for_v7.3_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: (24 commits) EDAC/thunderx: Orphan it EDAC/device_sysfs: Cleanup around edac_device_ctl_poll_msec_store() EDAC/device_sysfs: Use kstrtouint() for poll_msec to prevent truncation EDAC/igen6: Add Intel Starfire SoCs support EDAC/igen6: Refactor address translation logic EDAC/igen6: Remove redundant resource configuration tables EDAC/igen6: Detect present memory controllers at runtime EDAC/igen6: Simplify compute die ID comments EDAC/igen6: Remove unnecessary XOR on the zero-valued interleave bit EDAC/igen6: Fix Raptor Lake-P logged error address EDAC/igen6: Fix channel address decode for non-hash mode EDAC/igen6: Fix channel selection hash EDAC/igen6: Fix interleave boundary condition EDAC/ie31200: Decouple DIMM width decoding from enum order RAS/AMD/ATL: Remove conditional return with no effect EDAC: Remove redundant dev_err() MAINTAINERS: Add Radhey Shyam Pandey as Xilinx EDAC reviewer EDAC/altera: Remove remaining CONFIG_64BIT ifdefs in the DB-error path EDAC/altera: Use ECC manager compatible to select A10/S10 IRQ layout RAS/AMD/ATL, EDAC/amd64: Only load ATL when needed ... 2026-09-01T02:29:47+00:00 Borislav Petkov (AMD) bp@alien8.de 2026-09-01T02:29:47+00:00 urn:sha1:68c90773f40f91f48a557e9fa65e2a72cebc58df * ras/edac-misc: EDAC/thunderx: Orphan it EDAC/device_sysfs: Cleanup around edac_device_ctl_poll_msec_store() EDAC/device_sysfs: Use kstrtouint() for poll_msec to prevent truncation MAINTAINERS: Add Radhey Shyam Pandey as Xilinx EDAC reviewer MAINTAINERS: Remove Mark Gross from relevant entries EDAC/sysfs: Use sysfs_emit_at() in dimmdev_location_show() EDAC/mpc85xx: Orphan it * ras/edac-drivers: EDAC/igen6: Add Intel Starfire SoCs support EDAC/igen6: Refactor address translation logic EDAC/igen6: Remove redundant resource configuration tables EDAC/igen6: Detect present memory controllers at runtime EDAC/igen6: Simplify compute die ID comments EDAC/igen6: Remove unnecessary XOR on the zero-valued interleave bit EDAC/igen6: Fix Raptor Lake-P logged error address EDAC/igen6: Fix channel address decode for non-hash mode EDAC/igen6: Fix channel selection hash EDAC/igen6: Fix interleave boundary condition EDAC/ie31200: Decouple DIMM width decoding from enum order EDAC: Remove redundant dev_err() EDAC/altera: Remove remaining CONFIG_64BIT ifdefs in the DB-error path EDAC/altera: Use ECC manager compatible to select A10/S10 IRQ layout * ras/edac-amd-atl: RAS/AMD/ATL: Remove conditional return with no effect RAS/AMD/ATL, EDAC/amd64: Only load ATL when needed EDAC/debugfs: Remove the fake_inject debugfs interface Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> 2026-08-18T21:02:15+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-18T21:02:15+00:00 urn:sha1:8dcef8882aad8f1b8668d1c39968cde99312aa3c Pull x86 MSR updates from Ingo Molnar: - Streamline the x86 MSR handling APIs along the 64-bit variants, simplifying the interfaces. Removal of the old APIs is planned for the next cycle, to reduce churn & integration pain (Juergen Gross) * tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits) x86/mce: Work around build warning after MSR-interface switch cpufreq: Stop using 32-bit MSR interfaces x86/featctl: Stop using 32-bit MSR interfaces KVM/x86: Stop using 32-bit MSR interfaces x86/mtrr: Stop using 32-bit MSR interfaces acpi: Stop using 32-bit MSR interfaces powercap: Stop using 32-bit MSR interfaces thermal/intel: Stop using 32-bit MSR interfaces x86/olpc: Stop using 32-bit MSR interfaces x86/hyperv: Stop using 32-bit MSR interfaces hwmon: Stop using 32-bit MSR interfaces EDAC: Stop using 32-bit MSR interfaces x86/cpu: Stop using 32-bit MSR interfaces x86/apic: Stop using 32-bit MSR interfaces x86/resctrl: Stop using 32-bit MSR interfaces x86/tsc: Stop using 32-bit MSR interfaces x86/amd: Stop using 32-bit MSR interfaces x86/pci: Stop using 32-bit MSR interfaces x86/hygon: Stop using 32-bit MSR interfaces x86/mce: Stop using 32-bit MSR interfaces ... 2026-08-08T00:59:50+00:00 Borislav Petkov (AMD) bp@alien8.de 2026-08-08T00:59:50+00:00 urn:sha1:5464985e42c04e335fb30e38fbc409c997db9bec * ras/edac-misc: EDAC/device_sysfs: Cleanup around edac_device_ctl_poll_msec_store() EDAC/device_sysfs: Use kstrtouint() for poll_msec to prevent truncation Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> 2026-08-07T23:30:52+00:00 Borislav Petkov (AMD) bp@alien8.de 2026-08-07T21:16:17+00:00 urn:sha1:9987979189133486632842d894603813b22937e1 - Align function args - Fix comment style - Fixup formatting around edac_device_reset_delay_period() too The not-too-trivial change is converting the edac_device_reset_delay_period() msec argument to unsigned int as that is what the rest of the code expects. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> 2026-08-07T23:11:52+00:00 Jad Keskes inasj268@gmail.com 2026-07-30T14:55:48+00:00 urn:sha1:66cc9dec919dd63d8e4b3d386f7aed3ae684e645 The poll_msec sysfs store file uses simple_strtoul() which accepts an unsigned long, but the target field (poll_msec) is unsigned int. On 64-bit systems, a value > UINT_MAX is silently truncated when stored. Fix the mismatch by using kstrtouint() instead. This rejects values larger than UINT_MAX at parse time, making truncation impossible. Also add a check for value < 1 to reject the 0-delay case, which would cause the poll work to spin without delay and consume 100% CPU. Fixes: e27e3dac6517 ("drivers/edac: add edac_device class") Signed-off-by: Jad Keskes <inasj268@gmail.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20260730145549.148229-1-inasj268@gmail.com 2026-07-30T20:15:26+00:00 Tony Luck tony.luck@intel.com 2026-07-30T20:15:26+00:00 urn:sha1:b8dcf187035749d2528e4af4298830e64a9eb5f3 * edac-drivers EDAC/igen6: Add Intel Starfire SoCs support EDAC/igen6: Refactor address translation logic EDAC/igen6: Remove redundant resource configuration tables EDAC/igen6: Detect present memory controllers at runtime EDAC/igen6: Simplify compute die ID comments EDAC/igen6: Remove unnecessary XOR on the zero-valued interleave bit EDAC/igen6: Fix Raptor Lake-P logged error address EDAC/igen6: Fix channel address decode for non-hash mode EDAC/igen6: Fix channel selection hash EDAC/igen6: Fix interleave boundary condition EDAC/ie31200: Decouple DIMM width decoding from enum order Signed-off-by: Tony Luck <tony.luck@intel.com> 2026-07-30T18:34:12+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-07-30T02:54:54+00:00 urn:sha1:1713cc6b0e1904cf2c2b477ff25faf163c43cbdf Starfire is a derivative of Panther Lake SoC and shares a similar memory subsystem architecture. Add Starfire compute die ID and reuse Panther Lake's configuration data for EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Jie Wang <jie.wang@intel.com> Link: https://patch.msgid.link/20260730025454.4099934-1-qiuxu.zhuo@intel.com