kernel/git/next/linux-next.git/drivers/mtd, branch masterThe linux-next integration testing treehttps://git.landau.one/pub/scm/linux/kernel/git/next/linux-next.git/atom?h=master2026-09-08T15:20:51+00:00Merge branch 'spi-nor/next' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git2026-09-08T15:20:51+00:00Mark Brownbroonie@kernel.org2026-09-08T15:20:51+00:00urn:sha1:3ff4a5dd2276779efcd38cea9dc6a928a3dda43cMerge branch 'nand/next' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git2026-09-08T15:20:50+00:00Mark Brownbroonie@kernel.org2026-09-08T15:20:50+00:00urn:sha1:0b2cd09f043d0be34215e340e295d0b859b283f2Merge branch 'mtd/next' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git2026-09-08T15:20:48+00:00Mark Brownbroonie@kernel.org2026-09-08T15:20:48+00:00urn:sha1:45039b6bc03e816c880ca52dff97b3d6cd5159bfMerge branch 'mtd/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git2026-09-08T12:04:17+00:00Mark Brownbroonie@kernel.org2026-09-08T12:04:17+00:00urn:sha1:684226efa92d85465384b2ff7ffe6e2faf2fd87fmtd: spi-nor: debugfs: Expose SR opcodes and QE mask2026-09-07T07:45:22+00:00Miquel Raynalmiquel.raynal@bootlin.com2026-09-04T18:13:02+00:00urn:sha1:700bf34058ca7cd792236b1ba5caad3770d66208
Expose Status Register opcodes based on the flash capabilities
discovered while parsing the SFDP QER field.
Value '0' indicates an absence of opcode (non supported), we do not
print anything in that case.
The QE bit is also displayed.
Example on a W25Q02JV-M:
$ grep opcodes -A10 /sys/kernel/debug/spi-nor/spi0.0/params
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
SR1 read 0x05
SR2 read 0x35
SR1+SR2 write 0x01
QE SR2 bit 1
8D extension none
Tested-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
mtd: spi-nor: winbond: Add support for W25Q02RV-M2026-09-07T07:45:22+00:00Miquel Raynalmiquel.raynal@bootlin.com2026-09-04T18:13:01+00:00urn:sha1:4094a2fd562453cac04e909688af6620fbd3203f
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
mtd: spi-nor: winbond: Add support for W25Q01RV-M2026-09-07T07:45:22+00:00Miquel Raynalmiquel.raynal@bootlin.com2026-09-04T18:13:00+00:00urn:sha1:677a0d6752eda1480eae3e187c5dfe7367f9d752
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
mtd: spi-nor: winbond: Add support for W25Q51RV-M2026-09-07T07:45:22+00:00Miquel Raynalmiquel.raynal@bootlin.com2026-09-04T18:12:59+00:00urn:sha1:6397f5f8f8754218dd3a059d39eba6b57d04dc3d
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
mtd: spi-nor: winbond: Add support for W25Q25RV-M2026-09-07T07:45:22+00:00Miquel Raynalmiquel.raynal@bootlin.com2026-09-04T18:12:58+00:00urn:sha1:8eb8c80e59a3cde9fd7e4d730532668cb8ef7b0d
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
mtd: spi-nor: winbond: Add support for W25Q12RV-M2026-09-07T07:45:22+00:00Miquel Raynalmiquel.raynal@bootlin.com2026-09-04T18:12:57+00:00urn:sha1:11484eb5458fd54b59f35c511819af9e4de27cd1
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
This density wrongly advertizes its size and requires a fixup for
that.
Reviewed-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>