kernel/git/next/linux-next.git/drivers/pinctrl/qcom, branch master

Merge branch 'pinctrl-qcom/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git

2026-09-11T15:16:10+00:00

pinctrl: qcom: Add MSM8952 tlmm pinctrl driver

2026-09-09T12:52:13+00:00

MSM8952 has same pin count and similar pinctrl functions mostly with msm8917, but some functions use different pins. Signed-off-by: Muzaffer Kadir Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260907-msm8952-pinctrl-v5-2-9a2d8d72ffdb@mainlining.org Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: Drop marketing name-prefixed duplicate defines

2026-09-08T07:33:10+00:00

They are identical and of no use. Drop them and use the common MSM prefix. Assisted-by: LLM Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260907-topic-tlmm_define_cleanup-v1-1-accdf7859e4b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: ipq5210: Publish the OF module alias

2026-09-07T08:51:54+00:00

The IPQ5210 TLMM platform driver can be a module and matches through ipq5210_tlmm_of_match. This table is not published for OF modalias matching. Publish the existing table, preserving arch_initcall ordering and the shared MSM pinctrl probe. Fixes: a549fe22376f ("pinctrl: qcom: Introduce IPQ5210 TLMM driver") Signed-off-by: hpp.iscas Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260905134340.67477-1-hppiscas@163.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions

2026-09-07T07:55:50+00:00

QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 respectively. Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() stops at the first entry matching the requested function, which means mux value 1 was always selected and the I2C lanes could never be muxed out. In practice i2c9 and i2c10 got the UART lanes and did not work, while uart9 and uart10 happened to be muxed correctly. Give each lane pair its own function, following the _01/_23 naming already used for the same hardware arrangement by the shikra, eliza, hawi and maili TLMM drivers. Both functions still cover the full pin pair, so a single pinctrl state per protocol remains sufficient. Drop gpio129/gpio130 from the SE2 group list, since those pins belong to SE3 and were never reachable through the SE2 function. Also rename QUP1 SE2/SE3 functions in the binding doc accordingly. While at it, add missing "gpio", "qup3_se0_mira" and "qup3_se0_mirb" to the binding function enum to get the list complete. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Shawn Guo Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260830030201.135637-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: Add Kuno pinctrl driver

2026-09-02T10:26:36+00:00

Add the TLMM pinctrl driver for the Qualcomm Kuno platform, supporting 110 GPIOs and their pin multiplexing, pin configuration and gpiolib interface through the common pinctrl-msm driver. Signed-off-by: Hardeep Sharma Reviewed-by: Linus Walleij Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260827-kuno-soc-support-v5-9-6d47636a8f09@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: spmi-gpio: Add PMAU0102 GPIO support

2026-09-02T10:24:11+00:00

Add support for the PMAU0102 PMIC GPIO block, which has 12 GPIOs, used on Nord platform. Signed-off-by: Dhruvin Rajpura Signed-off-by: Shawn Guo Link: https://patch.msgid.link/20260830042939.144376-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: hawi-lpass-lpi: add Hawi LPASS LPI TLMM

2026-09-01T16:01:49+00:00

Add pin controller driver for the Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. The controller has 23 GPIOs with SoundWire, I2S, DMIC, VA I2S, ext_mclk1 and slimbus mux functions. Two pins (gpio13, gpio22) require 6 mux slots due to a test_bus entry occupying a middle hardware slot. Add LPI_PINGROUP6 macro to pinctrl-lpass-lpi.h to support pins with 5 alternate functions. Reviewed-by: Konrad Dybcio Signed-off-by: Prasad Kumpatla Link: https://patch.msgid.link/20260821113548.2686650-3-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2026-08-24T15:46:03+00:00

Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...

Merge tag 'pinctrl-qcom-updates-for-v7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel

2026-08-16T16:59:43+00:00

Qualcomm pinctrl updates for v7.3-rc1 New drivers: - add pinctrl drivers for Maili TLMM and Elize LPASS LPI TLMM controllers Driver updates: - acknowledge interrupts for the PDC interrupt controller in pinctrl-msm - implement irq_get/set_irqchip_state() for pinctrl-msm - add support for a new model to Qualcomm pinctrl-spmi-gpio - drop some dead code from qcom pinctrl modules Devicetree bindings: - document new TLMM controllers and the new model for the SPMI GPIO Signed-off-by: Linus Walleij