From a2ef401bdfd19aa41d0e3e1b630a12fbc01ac184 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Sep 2026 12:09:25 +0200 Subject: clk: rs9: Add clock index range check to rs9_of_clk_get() rs9_of_clk_get() does not validate the clock index in the passed DT clock specifier. If DT specifies an incorrect and out-of-range index, this will access memory beyond the end of the clk_dif[] array. Fix by this adding a range check to rs9_of_clk_get(). Fixes: 892e0ddea1aa6f70 ("clk: rs9: Add Renesas 9-series PCIe clock generator driver") Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Signed-off-by: Brian Masney --- drivers/clk/clk-renesas-pcie.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index 564550c80389..f3376c29007a 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -276,6 +276,11 @@ rs9_of_clk_get(struct of_phandle_args *clkspec, void *data) struct rs9_driver_data *rs9 = data; unsigned int idx = clkspec->args[0]; + if (idx >= rs9->chip_info->num_clks) { + pr_err("%s: Invalid clock index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + return rs9->clk_dif[idx]; } -- cgit v1.2.3