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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2026-07-13 16:05:33 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-09-07 17:37:24 +0200 |
| commit | 9206527c91b9f34e3e7cba0096c642e47d9c48c4 (patch) | |
| tree | c63f9210565259a787507eeced64d98d9451408d | |
| parent | de6aa7bd623fa90a27e7bb1d67a5bfc1ac9c34a5 (diff) | |
| download | linux-stable-9206527c91b9f34e3e7cba0096c642e47d9c48c4.tar.gz linux-stable-9206527c91b9f34e3e7cba0096c642e47d9c48c4.zip | |
i3c: renesas: Reset the controller on resume
commit 27cf0ad162f1a4526a86fc2ec24d84a4a98ac1dd upstream.
Reset the controller on resume after enabling the clocks to follow the
same sequence as in probe and avoid potential ordering related failures.
With it, renesas_i3c_reset() was updated to use read_poll_timeout_atomic(),
as the driver's resume callback is executed during the noirq phase of
resume, where interrupts are disabled.
Fixes: e7218986319b ("i3c: renesas: Add suspend/resume support")
Cc: stable@vger.kernel.org
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/20260713130545.568657-6-claudiu.beznea+renesas@tuxon.dev
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/i3c/master/renesas-i3c.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c index 4b6d8f46391d..6e1dc8e094db 100644 --- a/drivers/i3c/master/renesas-i3c.c +++ b/drivers/i3c/master/renesas-i3c.c @@ -494,8 +494,8 @@ static int renesas_i3c_reset(struct renesas_i3c *i3c) renesas_writel(i3c->regs, BCTL, 0); renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_RI3CRST); - return read_poll_timeout(renesas_readl, val, !(val & RSTCTL_RI3CRST), - 0, 1000, false, i3c->regs, RSTCTL); + return read_poll_timeout_atomic(renesas_readl, val, !(val & RSTCTL_RI3CRST), + 0, 1000, false, i3c->regs, RSTCTL); } static void renesas_i3c_hw_init(struct renesas_i3c *i3c) @@ -1489,6 +1489,10 @@ static int renesas_i3c_resume_noirq(struct device *dev) if (ret) goto err_presetn; + ret = renesas_i3c_reset(i3c); + if (ret) + goto err_clks_disable; + /* Re-store I3C registers value. */ renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(i3c->refclk_div)); @@ -1506,6 +1510,8 @@ static int renesas_i3c_resume_noirq(struct device *dev) return 0; +err_clks_disable: + clk_bulk_disable(i3c->num_clks, i3c->clks); err_presetn: reset_control_assert(i3c->presetn); err_tresetn: |