kernel/git/stable/linux.git/drivers/clk/qcom/Makefile, branch master

clk: qcom: Add support for videocc driver on Qualcomm Maili SoC

2026-07-31T03:37:12+00:00

Add support for Qualcomm Maili video clock controller driver for video clients to be able to request for videocc clocks. Reviewed-by: Konrad Dybcio Reviewed-by: Taniya Das Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260717-maili_videocc-v3-2-6656694b06a7@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC

2026-07-31T03:33:53+00:00

Add support for Audio Core Clock Controller (AUDIOCORECC) and Audio Core CSR resets on Qualcomm Shikra SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20260724-shikra-audiocorecc-v4-2-0a89bb13d817@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: gpucc: Add Nord graphics clock controller support

2026-07-31T03:32:40+00:00

Add support for the GPU clock controllers (GPUCC) on the Qualcomm Nord platform. The platform includes two GPU clock controller instances,GPUCC and GPU2CC. Register support for both controllers, which provide clocks required for the graphics subsystem. Reviewed-by: Alexandre Mergnat Reviewed-by: Shawn Guo Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-6-32b45232217f@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: Add Nord display clock controller support

2026-07-31T03:32:18+00:00

Add support for the display clock controllers (DISPCC) on the Qualcomm Nord platform. The platform includes two display clock controller instances, display0 and display1. Register support for both controllers. Reviewed-by: Konrad Dybcio Reviewed-by: Shawn Guo Signed-off-by: Taniya Das Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-4-32b45232217f@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: Add generic clkref_en support

2026-07-23T19:13:51+00:00

Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en register controls whether refclk is gated through to the PHY side. These clkref controls are different from typical GCC branch clocks: - only a single enable bit is present, without branch-style config bits - regulators must be voted before enable and unvoted after disable Model this as a dedicated clk_ref clock type with custom clk_ops instead of reusing struct clk_branch semantics. Also provide a common registration/probe API so the same clkref model can be reused regardless of where clkref_en registers are placed, e.g. TCSR on glymur and TLMM on SM8750. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Link: https://lore.kernel.org/r/20260721-tcsr_qre_0721-v10-3-d2fa68c63b78@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: camcc-glymur: Add camera clock controller driver

2026-07-11T15:20:18+00:00

Add support for the camera clock controller for camera clients to be able to request for camcc clocks on Glymur platform. Reviewed-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260624-glymur_camcc-v5-2-a321df74b1a1@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: Add Global clock controller support on Qualcomm Shikra SoC

2026-07-08T03:02:14+00:00

Add support for Global clock controller (GCC) on Qualcomm Shikra SoC. Reviewed-by: Taniya Das Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-4-94cefe092ee3@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: Add support for VideoCC driver for Hawi

2026-07-07T03:06:59+00:00

Enable Hawi video clock driver for video SW to be able to control the clocks from the Video SW driver. Reviewed-by: Konrad Dybcio Signed-off-by: Lin Li Link: https://lore.kernel.org/r/20260702-hawi-videocc-v1-2-6c1e640b0954@oss.qualcomm.com [bjorn: Added default m, per request from Krzysztof] Signed-off-by: Bjorn Andersson

clk: qcom: Add EVA clock controller driver for Glymur SoC

2026-07-07T02:59:00+00:00

Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-3-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson

clk: qcom: camcc-x1p42100: Add support for camera clock controller

2026-06-07T00:50:16+00:00

Add support for the camera clock controller for camera clients to be able to request for camcc clocks on X1P42100 platform. Although X1P42100 is derived from X1E80100, the camera clock controller driver differs significantly. Few PLLs, clocks and GDSC's are removed, there is delta in frequency tables for most RCG's and parent data structures also changed for few RCG's. Hence introduce a separate camcc driver for X1P42100 platform. Reviewed-by: Konrad Dybcio Reviewed-by: Taniya Das Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-5-fc3af4130282@oss.qualcomm.com Signed-off-by: Bjorn Andersson