kernel/git/stable/linux.git/drivers/pinctrl/intel/pinctrl-intel.c, branch master

pinctrl: intel: Remove redundant dev_err_probe()

2026-07-17T16:57:43+00:00

Since commit 55b48e23f5c4 ("genirq/devres: Add error handling in devm_request_*_irq()"), devm_request_irq() automatically logs detailed error messages on failure. Remove the now-redundant driver-specific dev_err_probe() calls. Signed-off-by: Pan Chuang Signed-off-by: Andy Shevchenko

pinctrl: intel: move PWM base computation past feature check

2026-05-18T07:01:17+00:00

Compute base inside intel_pinctrl_probe_pwm() only after the PINCTRL_FEATURE_PWM and CONFIG_PWM_LPSS checks have passed. Tidy up; no functional change. Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/linux-gpio/aglu5jy5SbW9Wjwj@ashevche-desk.local/ Signed-off-by: Stepan Ionichev Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: intel: Enable 3-bit PAD_OWN feature

2026-03-19T06:58:53+00:00

Starting from revision 1.1 of the Chassis specification the PAD_OWN is represented by 3 bits instead of 2 bits in the previous revisions. Update the driver to support this feature. Signed-off-by: Andy Shevchenko

pinctrl: intel: Fix the revision for new features (1kOhm PD, HW debouncer)

2026-03-19T06:58:53+00:00

The 1kOhm pull down and hardware debouncer are features of the revision 0.92 of the Chassis specification. Fix that in the code accordingly. Signed-off-by: Andy Shevchenko

pinctrl: intel: Improve capability support

2026-03-19T06:58:52+00:00

The register space of a certain capability starts at the offset just after the respective node in the capability list. It means that there are no fixed offsets for them from SoC to SoC generation and they have to be calculated at run-time. Improve capability support by adding the respective calculation algorithm and in the result enable PWM on more platforms that currently may use the wrong register. Signed-off-by: Andy Shevchenko

pinctrl: intel: Align Copyright note with corporate guidelines

2026-02-06T11:05:29+00:00

The Copyright note must follow the Copyright (C) Intel Corporation template, where (C) is always capitalised and either a single year or a range. Update the Intel pin control drivers to follow. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: intel: Remove duplicate error messages

2026-01-28T13:26:27+00:00

The pin control core is covered to report any error via message. Since that it's not needed in the callers. Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: intel: Export intel_gpio_add_pin_ranges()

2025-11-18T14:13:59+00:00

Export intel_gpio_add_pin_ranges() for reuse in other drivers. Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: intel: Unify messages with help of dev_err_probe()

2025-11-04T08:28:56+00:00

Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

treewide: rename GPIO set callbacks back to their original names

2025-08-07T08:07:06+00:00

The conversion of all GPIO drivers to using the .set_rv() and .set_multiple_rv() callbacks from struct gpio_chip (which - unlike their predecessors - return an integer and allow the controller drivers to indicate failures to users) is now complete and the legacy ones have been removed. Rename the new callbacks back to their original names in one sweeping change. Signed-off-by: Bartosz Golaszewski