<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/include/dt-bindings/pinctrl, branch linux-4.0.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/atom?h=linux-4.0.y</id>
<link rel='self' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/atom?h=linux-4.0.y'/>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/'/>
<updated>2015-03-06T17:21:03+00:00</updated>
<entry>
<title>ARM: dts: am43xx: fix SLEWCTRL_FAST pinctrl binding</title>
<updated>2015-03-06T17:21:03+00:00</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2015-02-28T01:10:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=10b218551444934b3ed864ec9eb81332d68d21ed'/>
<id>urn:sha1:10b218551444934b3ed864ec9eb81332d68d21ed</id>
<content type='text'>
According to AM437x TRM, Document SPRUHL7B, Revised December 2014,
Section 7.2.1 Pad Control Registers, setting bit 19 of the pad control
registers actually sets the SLEWCTRL value to slow rather than fast as
the current macro indicates. Introduce a new macro, SLEWCTRL_SLOW, that
sets the bit, and modify SLEWCTRL_FAST to 0 but keep it for
completeness.

Current users of the macro (i2c, mdio, and uart) are left unmodified as
SLEWCTRL_FAST was the macro used and actual desired state. Tested on
am437x-gp-evm with no difference in software performance seen.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: am33xx: fix SLEWCTRL_FAST pinctrl binding</title>
<updated>2015-03-06T17:12:56+00:00</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2015-02-28T01:10:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=424e0f039bfa8a51fb5c5178b6ece8baa4996469'/>
<id>urn:sha1:424e0f039bfa8a51fb5c5178b6ece8baa4996469</id>
<content type='text'>
According to AM335x TRM, Document spruh73l, Revised February 2015,
Section 9.2.2 Pad Control Registers, setting bit 6 of the pad control
registers actually sets the SLEWCTRL value to slow rather than fast as
the current macro indicates. Introduce a new macro, SLEWCTRL_SLOW, that
sets the bit, and modify SLEWCTRL_FAST to 0 but keep it for
completeness.

Current users of the macro (i2c and mdio) are left unmodified as
SLEWCTRL_FAST was the macro used and actual desired state. Tested on
am335x-gp-evm with no difference in software performance seen.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'sunxi-dt-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt</title>
<updated>2015-01-27T04:24:47+00:00</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2015-01-27T04:24:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=8749f9f3cfd961b9f4e1525de7b363e650562bb4'/>
<id>urn:sha1:8749f9f3cfd961b9f4e1525de7b363e650562bb4</id>
<content type='text'>
Merge "Allwinner device tree changes for 3.20" from Maxime Ripard:

A lot of changes to the device tree for the 3.20 merge window, mostly with:
  - More DT license convertions, only two DTS and two DTSI are still uncertain
    and have not been converted yet
  - Use the C-preprocessor includes in the device trees.
  - Add support for the A31s SoC and improve the A80 support
  - Add IR receiver, lradc, PS/2 support
  - Add cpufreq support for all SoCs but the A23 and A80.
  - And a lot of new boards

* tag 'sunxi-dt-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (64 commits)
  ARM: dts: sun5i: Enable axp209 support on A13-OLinuxIno
  ARM: sunxi: dts: Add A10/A20 PS2 pin muxing options
  ARM: sunxi: dts: Add PS2 nodes to dtsi for A10,A20
  ARM: dts: sun6i: Add resistive touchscreen controller node to dtsi
  ARM: dts: sun4i: Add Hyundau A7HD board
  ARM: dts: sun4i: Add Marsboard A10 board
  ARM: dts: sun9i: Enable mmc2 on A80 Optimus Board
  ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2
  ARM: dts: sun9i: Enable mmc0 on A80 Optimus Board
  ARM: dts: sun9i: Convert a80 optimus board dts to label referencing
  ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi
  ARM: dts: sun9i: Add mmc config clock nodes
  ARM: dts: sunxi: Add missing mdio label
  ARM: dts: sun5i: Add mk802_a10s board
  ARM: dts: sun4i: Add mk802ii board
  ARM: dts: sun4i: Add mk802 board
  ARM: dts: sun4i: Add dts file for Chuwi V7 CW0825 tablet
  ARM: dts: sun7i: Add dts file for Bananapro board
  ARM: sun6i: Enable ARM arch timers
  ARM: dts: sun6i: Convert hummingbird a31 dts to label references
  ...

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodes</title>
<updated>2015-01-21T08:58:57+00:00</updated>
<author>
<name>Maxime Ripard</name>
<email>maxime.ripard@free-electrons.com</email>
</author>
<published>2014-12-16T21:59:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=092a0c3b18ce8f2207591846dad5c9071ed2f832'/>
<id>urn:sha1:092a0c3b18ce8f2207591846dad5c9071ed2f832</id>
<content type='text'>
The pinctrl nodes require some extra opaque arguments for the pull up and drive
strength values.

Introduce a new header file and convert the device trees to replace these
opaque numbers by defines.

Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: Add minimal support for dm8168-evm</title>
<updated>2015-01-19T19:47:35+00:00</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2015-01-19T19:47:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=ac7452cee7430ea507ddf70700de56482f15dae3'/>
<id>urn:sha1:ac7452cee7430ea507ddf70700de56482f15dae3</id>
<content type='text'>
This allows booting the device with basic functionality.

Note that at least on my revision c board the DDR3 does
not seem to work properly and only some of the memory
can be reliably used.

Also, the mainline u-boot does not seem to properly
initialize the ethernet, so I've been using the old TI
u-boot at:

http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=summary

Cc: Brian Hutchinson &lt;b.hutchman@gmail.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2014-12-11T18:43:14+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2014-12-11T18:43:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=c1b30e4d9466000c0e287e9245d4397da4d7d2f9'/>
<id>urn:sha1:c1b30e4d9466000c0e287e9245d4397da4d7d2f9</id>
<content type='text'>
Pull pin control changes from Linus Walleij:
 "Here is a stash of pin control changes I have collected for the v3.19
  series.  Mainly new hardware support, with Intels new embedded SoC as
  the especially interesting thing standing out, fully using the
  subsystem.

   - Force conversion of the ux500 pin control device trees and parsers
     to use the generic pin control bindings.
   - New driver and device tree bindings for the Qualcomm PMIC MPP pin
     controller and GPIO.
   - Some ACPI infrastructure for pin controllers.
   - New driver for the Intel CherryView/Braswell pin controller, the
     first Intel pin controller to fully take advantage of the pin
     control subsystem.
   - Support the Freescale i.MX VF610 variant.
   - Support the sunxi A80 variant.
   - Support the Samsung Exynos 4415 and Exynos 7 variants.
   - Split out Intel pin controllers to their own subdirectory.
   - A large slew of rockchip pin control updates, including
     suspend/resume support.
   - A large slew of Samsung Exynos pin controller updates.
   - Various minor updates and fixes"

* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
  pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
  pinctrl: meson: add device tree bindings documentation
  gpio: tz1090: Fix error handling of irq_of_parse_and_map
  pinctrl: tz1090-pinctrl.txt: Fix typo in binding
  pinctrl: pinconf-generic: Declare dt_params/conf_items const
  pinctrl: exynos: Add support for Exynos4415
  pinctrl: exynos: Add initial driver data for Exynos7
  pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
  pinctrl: exynos: Consolidate irq domain callbacks
  pinctrl: exynos: Generalize the eint16_31 demux code
  pinctrl: samsung: Separate per-bank init and runtime data
  pinctrl: samsung: Constify samsung_pin_ctrl struct
  pinctrl: samsung: Constify samsung_pin_bank_type struct
  pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
  pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
  pinctrl: Add Intel Cherryview/Braswell pin controller support
  gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
  pinctrl: Fix path error in documentation
  pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
  pinctrl: rockchip: add suspend/resume functions
  ...
</content>
</entry>
<entry>
<title>pinctrl: dra: dt-bindings: Fix output pull up/down</title>
<updated>2014-11-10T22:29:20+00:00</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2014-11-03T10:09:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=73b3a6657a88ef5348a0d69c9a8107d6f01ae862'/>
<id>urn:sha1:73b3a6657a88ef5348a0d69c9a8107d6f01ae862</id>
<content type='text'>
For PIN_OUTPUT_PULLUP and PIN_OUTPUT_PULLDOWN we must not set the
PULL_DIS bit which disables the PULLs.

PULL_ENA is a 0 and using it in an OR operation is a NOP, so don't
use it in the PIN_OUTPUT_PULLUP/DOWN macros.

Fixes: 23d9cec07c58 ("pinctrl: dra: dt-bindings: Fix pull enable/disable")

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
Acked-by: Nishanth Menon &lt;nm@ti.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: Device tree bindings for Qualcomm PMIC MPP block</title>
<updated>2014-10-29T08:28:36+00:00</updated>
<author>
<name>Ivan T. Ivanov</name>
<email>iivanov@mm-sol.com</email>
</author>
<published>2014-10-22T09:58:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=89a7117d56d405b49b7d1f8ed30e01188e9d5a05'/>
<id>urn:sha1:89a7117d56d405b49b7d1f8ed30e01188e9d5a05</id>
<content type='text'>
DeviceTree binding documentation for Qualcomm SPMI PMIC MPP
pinctrl drivers.

Signed-off-by: Ivan T. Ivanov &lt;iivanov@mm-sol.com&gt;
Acked-by: Bjorn Andersson &lt;bjorn.andersson@sonymobile.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Device tree bindings for Qualcomm PMIC GPIO block</title>
<updated>2014-10-29T08:28:36+00:00</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@sonymobile.com</email>
</author>
<published>2014-10-22T09:58:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=43059f6ba21177f25ab1b10f95149cff1895806a'/>
<id>urn:sha1:43059f6ba21177f25ab1b10f95149cff1895806a</id>
<content type='text'>
This introduced the device tree bindings for the GPIO block found
in PMIC's from Qualcomm.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@sonymobile.com&gt;
Signed-off-by: Ivan T. Ivanov &lt;iivanov@mm-sol.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: at91: add drive strength configuration</title>
<updated>2014-09-05T08:32:06+00:00</updated>
<author>
<name>Marek Roszko</name>
<email>mark.roszko@gmail.com</email>
</author>
<published>2014-08-24T03:12:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=4334ac2db2be9e278c95fd15260c1f49f698ffc5'/>
<id>urn:sha1:4334ac2db2be9e278c95fd15260c1f49f698ffc5</id>
<content type='text'>
The SAMA5 and SAM9x5 series both have drive strength
options for the PIOs. This patch adds the ability to set
one of three hardware options for drive strengths of low,
medium or high for the each pin. The actual current output
of the chip based on the setting is defined in the datasheets
and varies per pins separate from banks and with supply
voltage.

This patch adds three new dt-bindings that allow setting the
strength when configuring pins. By default, no change will
be made to the drive strength of a pin from its reset value.
Due to the difference between the register addresses of the
SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added.

Signed-off-by: Marek Roszko &lt;mark.roszko@gmail.com&gt;
Acked-by: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
