<feed xmlns='http://www.w3.org/2005/Atom'>
<title>software/src/opensbi.git/include, branch master</title>
<subtitle>RISC-V Open Source Supervisor Binary Interface</subtitle>
<id>https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/atom?h=master</id>
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<updated>2026-09-05T07:23:15+00:00</updated>
<entry>
<title>lib: sbi_domain: Rename per-domain data to per-domain state</title>
<updated>2026-09-05T07:23:15+00:00</updated>
<author>
<name>Rahul Pathak</name>
<email>rahul.pathak@oss.qualcomm.com</email>
</author>
<published>2026-08-20T12:13:09+00:00</published>
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<id>urn:sha1:3593a5facc4c6938b90429a6973ba9ee21fc5899</id>
<content type='text'>
The per-domain sbi_domain_data hold each domain
associated state like hart context in sbi_domain_context,
mpxy state in sbi_mpxy, and others like each domain backed
by the corresponding MPT (SMMPT).
DATA reads as a generic name, while every use stores state.
Rename functions and macros appropriately. There are no
functional changes.

Signed-off-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260820121309.2551296-3-rahul.pathak@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Rename map_range/unmap_range functions</title>
<updated>2026-09-05T07:22:39+00:00</updated>
<author>
<name>Rahul Pathak</name>
<email>rahul.pathak@oss.qualcomm.com</email>
</author>
<published>2026-08-20T12:13:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=35af7c8c7ee00869afc6e9e0aca64086888bd03f'/>
<id>urn:sha1:35af7c8c7ee00869afc6e9e0aca64086888bd03f</id>
<content type='text'>
*_map_range and *_unmap_range functions are required
in M-Mode to get the temporary access to S-Mode and U-Mode
regions. Thse functions only operate using the TYPE_MEMORY
memory protection mechanisms. Rename them to reflect the
actual usage of these functions and let generic map/unmap_range
names to implement generic functions

Signed-off-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Pawandeep Oza &lt;pawandeep.oza@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260820121309.2551296-2-rahul.pathak@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Fix counter and event info error codes as per SBI v3.0 spec</title>
<updated>2026-09-04T06:13:53+00:00</updated>
<author>
<name>David E. Garcia Porras</name>
<email>david.garcia@aheadcomputing.com</email>
</author>
<published>2026-08-18T21:00:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=c5077d497d0f7c7c9a74218ef2c448bc1a6d8a31'/>
<id>urn:sha1:c5077d497d0f7c7c9a74218ef2c448bc1a6d8a31</id>
<content type='text'>
Align the PMU extension implementation with the error codes required
by the SBI v3.0 specification, chapter 11:

 - sbi_pmu_counter_start and sbi_pmu_counter_stop (secs 11.9-11.10,
   tables 39-42): the start_flags/stop_flags bits 2:(XLEN-1) are
   reserved and must be zero, so return SBI_ERR_INVALID_PARAM when any
   reserved flag bit is set. Introduce SBI_PMU_START_FLAGS_MASK and
   SBI_PMU_STOP_FLAGS_MASK for the valid bits of each function.

 - sbi_pmu_counter_start and sbi_pmu_counter_stop (tables 40 and 42):
   return SBI_ERR_ALREADY_STARTED / SBI_ERR_ALREADY_STOPPED when the
   set of counters includes a counter which is already started or
   stopped, instead of ignoring the error returned for each counter.

 - sbi_pmu_event_get_info (sec 11.14, table 47): the output word must
   indicate whether the event is supported, but firmware events were
   only matched against the hardware event map and were always
   reported as unsupported. Report a validated firmware event as
   supported.

Signed-off-by: David E. Garcia Porras &lt;david.garcia@aheadcomputing.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260818210023.466462-4-david.garcia@aheadcomputing.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Return invalid param error for reserved event_idx bits</title>
<updated>2026-09-03T07:57:45+00:00</updated>
<author>
<name>David E. Garcia Porras</name>
<email>david.garcia@aheadcomputing.com</email>
</author>
<published>2026-08-18T21:00:21+00:00</published>
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<id>urn:sha1:d97cfb33ae1ac0d9eebce1a03c96497a1f8f4c67</id>
<content type='text'>
As per section 11.14 of the SBI specification (Function: Get PMU Event
Info, FID #8), Table 47, the event_idx word of an event info entry
only uses BIT[0:19]; BIT[20:31] are reserved for the future purpose
and must be zero. Table 48 further requires the SBI implementation to
return SBI_ERR_INVALID_PARAM if any reserved bit in an event_idx word
is set.

sbi_pmu_event_get_info() does not check the reserved bits, so a
malformed event_idx is silently passed on to pmu_event_validate()
instead of failing the call. Add SBI_PMU_EVENT_IDX_MBZ_MASK covering
the must-be-zero bits and return SBI_ERR_INVALID_PARAM when any of
them are set.

Fixes: e4345842168b ("lib: sbi_pmu: Implement SBI PMU event info function")
Signed-off-by: David E. Garcia Porras &lt;david.garcia@aheadcomputing.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260818210023.466462-2-david.garcia@aheadcomputing.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/suspend: wait for the secondary Andes harts to sleep</title>
<updated>2026-09-01T05:16:23+00:00</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2026-07-28T08:10:40+00:00</published>
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<id>urn:sha1:0fb479930775cf86efdfd5c50ad21b4cf8353c76</id>
<content type='text'>
A secondary hart may not have reached the target sleep state by the time
the primary checks, so the one-shot check could fail spuriously. Poll
each PCS status instead and give up after HART_SLEEP_TIMEOUT_MS.

Rework atcsmu_pcs_is_sleep() into the atcsmu_hart_is_sleep() predicate so
sbi_timer_waitms_until() can drive it.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260728081041.2724668-7-ben717@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/hsm: wake sleeping Andes harts with an IPI</title>
<updated>2026-09-01T05:16:23+00:00</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2026-07-28T08:10:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=e01bd7926b5d808d883df18c6ac919dfa9ab04e7'/>
<id>urn:sha1:e01bd7926b5d808d883df18c6ac919dfa9ab04e7</id>
<content type='text'>
An IPI wakes a hart from light sleep and, once MSIP is kept as an SMU
wakeup event, from deep sleep too. Drop the WAKEUP_CMD path and the boot
state, hart type and sleep type conditions that selected it.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260728081041.2724668-6-ben717@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: dbtr: add platform device for per-slot trigger capabilities</title>
<updated>2026-09-01T05:06:07+00:00</updated>
<author>
<name>David E. Garcia Porras</name>
<email>david.garcia@aheadcomputing.com</email>
</author>
<published>2026-07-27T18:30:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=27d954538410a7fbecf0ed68ce319706d3e3b142'/>
<id>urn:sha1:27d954538410a7fbecf0ed68ce319706d3e3b142</id>
<content type='text'>
The tinfo probe only discovers trigger types; WARL fields tied off
inside an implemented trigger CSR (e.g. an mcontrol6 trigger without
load/store address match) are not discoverable. sbi_alloc_trigger()
also selects the first free trigger slot irrespective of the requested
trigger type or configuration. Unsupported configurations are thus
silently dropped by the hardware while SBI reports success, where SBI
v3.0 sections 19.4 / 19.5 require SBI_ERR_NOT_SUPPORTED.

Add an optional platform device, struct sbi_dbtr_device, with a
trigger_supported(idx, tdata1, tdata2, tdata3) callback reporting
whether the trigger slot selected by idx (the tselect value) supports
a given configuration. Use it, together with the probed per-slot
type_mask, to:

  - allocate only trigger slots supporting the requested configuration
    (new dbtr_find_free_slot() helper)
  - reject unsupportable install/update requests with
    SBI_ERR_NOT_SUPPORTED
  - count only supporting slots in sbi_dbtr_num_trig() (SBI v3.0
    section 19.1)

The install path now dry-runs the allocation of the whole batch before
programming any trigger, so a partially-installed batch is never left
behind. Without a registered device, only the type matching applies (unchanged behavior).

Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support")
Signed-off-by: David E. Garcia Porras &lt;david.garcia@aheadcomputing.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260727183041.258377-2-david.garcia@aheadcomputing.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Allow platforms to override local TLB operations</title>
<updated>2026-08-20T15:00:48+00:00</updated>
<author>
<name>Xiang W</name>
<email>wangxiang@iscas.ac.cn</email>
</author>
<published>2026-06-17T11:29:26+00:00</published>
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<id>urn:sha1:f465413402c53fd022d54c3e56a26f96cdc32ffc</id>
<content type='text'>
Some T-Head based processors, for example the Sophgo SG2044, have a
JTLB errata that requires special handling of certain TLB maintenance
instructions (sfence.vma).

Introduce a sbi_tlb_local_operations structure so platforms can provide
custom local TLB flush implementations. Use it to implement the JTLB
workaround on affected SoCs (currently Sophgo SG2044).

Signed-off-by: Xiang W &lt;wangxiang@iscas.ac.cn&gt;
Signed-off-by: Han Gao &lt;gaohan@iscas.ac.cn&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260617112925.1144190-2-wangxiang@iscas.ac.cn
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib/sbi/sbi_timer: Add sbi_timer_frequency() function</title>
<updated>2026-08-20T12:27:45+00:00</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@oss.qualcomm.com</email>
</author>
<published>2026-07-03T05:05:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=6499c022541fd85e2eee8fc93951ebe212b494e8'/>
<id>urn:sha1:6499c022541fd85e2eee8fc93951ebe212b494e8</id>
<content type='text'>
Drivers and other library code sometimes need the timer frequency
outside of lib/sbi/sbi_timer.c, but there is currently no accessor
for it. Add sbi_timer_frequency() to expose the frequency of the
registered timer device.

Signed-off-by: Sunil V L &lt;sunilvl@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260703050530.2460037-2-sunilvl@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: make SBI_HARTMASK_MAX_BITS customizable, default 256</title>
<updated>2026-08-20T12:27:19+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2026-07-06T16:05:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=3876e7574dd7eff9241e6fb0a3822e4e51731b9f'/>
<id>urn:sha1:3876e7574dd7eff9241e6fb0a3822e4e51731b9f</id>
<content type='text'>
Linux has raised the default number of 64bit CPUs to 256 in commit
0fa749771993 ("riscv: Raise default NR_CPUS for 64BIT to 256").
OpenSBI should use a matching value for SBI_HARTMASK_MAX_BITS.

Introduce configuration variable CONFIG_HARTMASK_MAX_BITS with
range 32-512 and default 256.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260706160544.697409-1-heinrich.schuchardt@canonical.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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