<feed xmlns='http://www.w3.org/2005/Atom'>
<title>software/src/opensbi.git/lib/sbi/sbi_hart_protection.c, branch master</title>
<subtitle>RISC-V Open Source Supervisor Binary Interface</subtitle>
<id>https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/atom?h=master</id>
<link rel='self' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/'/>
<updated>2026-09-05T07:22:39+00:00</updated>
<entry>
<title>lib: sbi: Rename map_range/unmap_range functions</title>
<updated>2026-09-05T07:22:39+00:00</updated>
<author>
<name>Rahul Pathak</name>
<email>rahul.pathak@oss.qualcomm.com</email>
</author>
<published>2026-08-20T12:13:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=35af7c8c7ee00869afc6e9e0aca64086888bd03f'/>
<id>urn:sha1:35af7c8c7ee00869afc6e9e0aca64086888bd03f</id>
<content type='text'>
*_map_range and *_unmap_range functions are required
in M-Mode to get the temporary access to S-Mode and U-Mode
regions. Thse functions only operate using the TYPE_MEMORY
memory protection mechanisms. Rename them to reflect the
actual usage of these functions and let generic map/unmap_range
names to implement generic functions

Signed-off-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Pawandeep Oza &lt;pawandeep.oza@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260820121309.2551296-2-rahul.pathak@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Print list of all hart protection mechanisms at boot time</title>
<updated>2026-08-02T09:47:12+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-07-27T04:25:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=337c23dd66b821ac04a0f7bea313e7e7b30ecc49'/>
<id>urn:sha1:337c23dd66b821ac04a0f7bea313e7e7b30ecc49</id>
<content type='text'>
Instead of printing only the best hart memory protection name at
boot time let's print a list of all hart projection mechanisms.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Reviewed-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260727042504.1743250-6-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Extend hart protection abstraction to allow ID configuration</title>
<updated>2026-08-02T09:47:12+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-07-27T04:25:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=2636a9c2a827e07e29777bffd29ac05254f0bfeb'/>
<id>urn:sha1:2636a9c2a827e07e29777bffd29ac05254f0bfeb</id>
<content type='text'>
There are various ID configuration ISA extensions such as RISC-V Worlds,
Supervisor domain ID, QoS ID, etc which need to be re-configured upon
domain context switch on a hart. Extend hart protection abstraction to
support both memory protection and ID configuration ISA extensions.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Reviewed-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260727042504.1743250-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add domain parameter to hart protection (un)configure()</title>
<updated>2026-08-02T09:47:12+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-07-27T04:25:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=5053774c2f21029089a58ccadf21b5b3cb16c56e'/>
<id>urn:sha1:5053774c2f21029089a58ccadf21b5b3cb16c56e</id>
<content type='text'>
The switch_to_next_domain_context() already has the pointers to current
and next domains so pass them as parameters to hart protection configure()
and unconfigure() callbacks.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Reviewed-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260727042504.1743250-4-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Introduce sbi_hart_protection_reconfigure() function</title>
<updated>2026-08-02T09:47:12+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-07-27T04:25:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=48725e95b4d02281bee268f6a9f8b5a77eb001fb'/>
<id>urn:sha1:48725e95b4d02281bee268f6a9f8b5a77eb001fb</id>
<content type='text'>
Instead of assuming that hart protection reconfiguration is unconfigure
followed by configure, introduce a separate sbi_hart_protection_reconfigure()
function and use it in switch_to_next_domain_context().

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Reviewed-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260727042504.1743250-3-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Fix behavior on platform without HART protection</title>
<updated>2026-01-08T08:48:14+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2026-01-07T16:04:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=74434f255873d74e56cc50aa762d1caf24c099f8'/>
<id>urn:sha1:74434f255873d74e56cc50aa762d1caf24c099f8</id>
<content type='text'>
The commit 42139bb9b7dc ("lib: sbi: Replace sbi_hart_pmp_xyz() and
sbi_hart_map/unmap_addr()") changed logic by calling
sbi_hart_protection_configure(). But when protection doesn't exist
the function is returning SBI_EINVAL.
But on systems without protection this is correct configuration
that's why do not hang when system don't have any HART protection.

Fixes: 42139bb9b7dc ("lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()")
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/bb8641e5f82654e3989537cea85f165f67a7044e.1767801896.git.michal.simek@amd.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Introduce hart protection abstraction</title>
<updated>2025-12-16T14:46:47+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2025-12-09T13:52:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.landau.one/pub/scm/riscv/software/src/opensbi.git/commit/?id=809df05c35ae20d6b68676c24640f92fa0e2666c'/>
<id>urn:sha1:809df05c35ae20d6b68676c24640f92fa0e2666c</id>
<content type='text'>
Currently, PMP and ePMP are the only hart protection mechanisms
available in OpenSBI but new protection mechanisms (such as Smmpt)
will be added in the near future.

To allow multiple hart protection mechanisms, introduce hart
protection abstraction and related APIs.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20251209135235.423391-3-apatel@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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