qemu/qemu.git/include/hw/misc/aspeed_sbc.h, branch master

hw/arm/aspeed_ast10x0: Wire SEC SRAM to the SBC model

2026-09-05T05:05:11+00:00

Introduce the "has_ecdsa" class attribute and enable it for the AST10x0 SBC, as ECDSA is only supported on this platform. Add an "sram" link property to the SBC model and initialize a dedicated address space for accessing the SEC SRAM. This will be used by the ECDSA verify command to read the public key, signature, and digest from SRAM. Wrap the SEC SRAM in a container mapped at offset 0. This allows the ECDSA engine added in a later patch to access the SRAM using relative offsets without requiring the SBC model to know the SRAM's system address. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20260901085238.995968-8-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater

hw/misc/aspeed_sbc: Increase register space to 0x1000

2026-09-05T05:05:11+00:00

The SBC controller register space is 0x1000. Increase ASPEED_SBC_NR_REGS accordingly to cover the full register space. This changes the size of the VMState register array and therefore breaks migration compatibility with older QEMU versions. Simply bump the VMState version to 2, as Aspeed machines are not intended for virtualization use cases. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20260901085238.995968-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater

include: move hw/sysbus.h to hw/core/

2025-12-27T09:11:08+00:00

Signed-off-by: Paolo Bonzini

hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs

2025-09-29T16:00:20+00:00

The has_otp attribute is enabled in the SBC subclasses for AST1030 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-7-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater

hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC

2025-09-29T16:00:20+00:00

This patch connects the aspeed.otp device to the ASPEED Secure Boot Controller (SBC) model. It implements OTP memory access via the SBC's command interface and enables emulation of secure fuse programming flows. The following OTP commands are supported: - READ: reads a 32-bit word from OTP memory into internal registers - PROG: programs a 32-bit word value to the specified OTP address Trace events are added to observe read/program operations and command handling flow. Signed-off-by: Kane-Chen-AS Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-3-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater

aspeed: sbc: Allow per-machine settings

2022-07-14T14:24:38+00:00

In order to correctly report secure boot running firmware the values of certain registers must be set. We don't yet have documentation from ASPEED on what they mean. The meaning is inferred from u-boot's use of them. Introduce properties so the settings can be configured per-machine. Reviewed-by: Peter Delevoryas Tested-by: Peter Delevoryas Signed-off-by: Joel Stanley Message-Id: <20220628154740.1117349-4-clg@kaod.org> Signed-off-by: Cédric Le Goater

Clean up decorations and whitespace around header guards

2022-05-11T14:50:32+00:00

Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson

ast2600: Add Secure Boot Controller model

2022-02-26T17:40:51+00:00

Just a stub that indicates the system has booted in secure boot mode. Used for testing the driver: https://lore.kernel.org/all/20211019080608.283324-1-joel@jms.id.au/ Signed-off-by: Joel Stanley [ clg: - Fixed typo - Adjusted Copyright dates ] Signed-off-by: Cédric Le Goater