qemu/qemu.git/target/mips, branch master

target/mips: Constify CPUMIPSState for various cpu_*() getters

2026-09-03T10:14:08+00:00

Add the const qualifier to CPUMIPSState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Marc-André Lureau Message-Id: <20260901095229.72018-14-philmd@oss.qualcomm.com>

target/mips: Enable disassembly via capstone

2026-08-19T00:35:33+00:00

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

target/mips: Expand octeon reflections inline

2026-08-19T00:31:48+00:00

Use tcg_gen_revbit64_i64 instead of out-of-line helpers. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson

hw/cpu: Rename cpu_exec_realizefn() -> cpu_common_realize()

2026-08-16T14:32:41+00:00

Keep cpu_common_*() pattern for publicly exposed common methods used by target code. Use cpu_exec_*() pattern for internal ones, mostly to distinct between system / user mode. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20260811183410.22428-6-philmd@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé

target/mips: add Octeon CvmCount RDHWR support

2026-07-07T18:14:46+00:00

Octeon exposes CvmCount through RDHWR register 31. Add the Octeon-only decode path, enable the corresponding HWREna bit for linux-user, and use an unsigned mask when checking HWREna so bit 31 is handled safely. For user-mode emulation, return host ticks as a monotonic counter source suitable for existing Octeon userspace code. In system mode, fall back to the existing CP0 Count value. Reviewed-by: Richard Henderson Signed-off-by: James Hilliard Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-20-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

target/mips: decode Octeon CHORD and LLM COP2 selectors

2026-07-07T18:14:46+00:00

Add explicit decodetree entries and translator bindings for the Octeon CHORD and sparse LLM COP2 selectors. CHORD and LLM use their own COP2 selector window rather than the crypto engine windows covered by the preceding decode patches. This completes the explicit COP2 selector coverage by adding the remaining CHORD and LLM register and operation selectors. Signed-off-by: James Hilliard Acked-by: Richard Henderson Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-19-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

target/mips: decode Octeon block-cipher COP2 selectors

2026-07-07T18:14:46+00:00

Add explicit decodetree entries and translator bindings for the Octeon AES, SMS4, 3DES, KASUMI, and Camellia COP2 operation selectors. These selectors consume or update engine state, so keep them as per-operation helper calls while the simple block-cipher register moves remain direct TCG loads and stores from the earlier register-selector patch. This completes the block-cipher selector coverage without reintroducing a generic runtime selector dispatch path. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-18-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

target/mips: decode Octeon ZUC and SNOW3G COP2 selectors

2026-07-07T18:14:46+00:00

Add explicit decodetree entries and translator bindings for the Octeon ZUC and SNOW3G COP2 operation selectors. These stream-cipher selectors operate on the shared HSH register window state, so dispatch them through the per-operation helpers added with the corresponding engine support. Keep stream-cipher decode separate because these selectors share the HSH register window with unrelated engines. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-17-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

target/mips: decode Octeon HSH and SHA3 COP2 selectors

2026-07-07T18:14:46+00:00

Add explicit decodetree entries and translator bindings for the Octeon HSH shared-window selectors and SHA3 operation selectors. Simple SHA3 DAT register moves and XORDAT selectors use direct TCG transfers, while HSH operation selectors and SHA3 STARTOP remain helper-backed for their visible side effects. Keep HSH/SHA3 decode separate from direct register transfers because the shared hash-window aliases and side-effecting operations need their own selector coverage. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-16-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

target/mips: decode Octeon CRC and GFM COP2 selectors

2026-07-07T18:14:46+00:00

Add explicit decodetree entries and translator bindings for the Octeon CRC and GFM COP2 operation selectors. Unlike simple register moves, these selectors update CRC or Galois-field state and therefore remain per-operation helper calls. Keep CRC/GFM decode next to the helpers that implement these side effects while avoiding a monolithic selector-dispatch helper. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-15-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé