diff options
| author | Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> | 2026-05-22 15:13:53 -0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2026-06-16 22:38:15 +0300 |
| commit | 2b8147e7198a97fc0191bd78a413cf1d8705e6f9 (patch) | |
| tree | 821c7d21b24817439002799e019f01beb24e82a5 | |
| parent | 99685f9b0f50e42afb818d6e3f9fe893705c3c80 (diff) | |
| download | qemu-2b8147e7198a97fc0191bd78a413cf1d8705e6f9.tar.gz qemu-2b8147e7198a97fc0191bd78a413cf1d8705e6f9.zip | |
target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault
promote_load_fault() is missing the promotion of misaligned AMO load
addresses, i.e. RISCV_EXCP_LOAD_ADDR_MIS should be promoted to
RISCV_EXCP_STORE_AMO_ADDR_MIS when RISCV_UW2_ALWAYS_STORE_AMO (i.e.
always_storeamo is true).
All other load AMO faults are already being covered.
Cc: qemu-stable@nongnu.org
Fixes: 98f21c30f5 ("target/riscv: AMO operations always raise store/AMO fault")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3503
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Message-ID: <20260522181353.429782-1-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit d85a4ec06a65ccdd5c7d0f00b3e6695fc14a547a)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | target/riscv/cpu_helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 024213fb4b..1bd6649f23 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2124,6 +2124,9 @@ static target_ulong promote_load_fault(target_ulong orig_cause) case RISCV_EXCP_LOAD_PAGE_FAULT: return RISCV_EXCP_STORE_PAGE_FAULT; + + case RISCV_EXCP_LOAD_ADDR_MIS: + return RISCV_EXCP_STORE_AMO_ADDR_MIS; } /* if no promotion, return original cause */ |