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| author | TANG Tiancheng <lyndra@linux.alibaba.com> | 2026-07-03 13:03:37 +0800 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2026-08-25 10:27:16 +0300 |
| commit | 4f07934c4e6af1b2bf8ec0ab62bbf8076d810478 (patch) | |
| tree | 2839b322c4e0ed0812f22df914bfb5e22986d869 | |
| parent | b346ba5889bcfd59c8dbd3c79c16015d9154cdd3 (diff) | |
| download | qemu-4f07934c4e6af1b2bf8ec0ab62bbf8076d810478.tar.gz qemu-4f07934c4e6af1b2bf8ec0ab62bbf8076d810478.zip | |
disas/riscv: Fix 6-bit immediate extraction
rv_codec_r2_imm6 is used for XThead instructions whose 6-bit
immediate field is encoded in bits 25:20. The old expression
left-shifted by 38 and then right-shifted by 60, so it kept only
bits 25:22.
Use extract32() to decode bits 25:20 directly. This fixes the
immediate printed for th.srri and th.tst.
Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* instructions")
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260703-b4-disas-xthead-fix-riscv-next-v4-2-84c566330bc7@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 7a8454ef293085a45686929577b7d5a5daded242)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | disas/riscv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index 5a61d1bb80..2de092ed92 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4538,7 +4538,7 @@ static uint32_t operand_zcmp_rlist(rv_inst inst) static uint32_t operand_imm6(rv_inst inst) { - return (inst << 38) >> 60; + return extract32(inst, 20, 6); } static uint32_t operand_imm2(rv_inst inst) |