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| author | Joel Stanley <joel@jms.id.au> | 2026-08-13 12:54:14 +0930 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2026-08-24 22:01:01 +0300 |
| commit | 2c0db8a985e7ee2740b16fc7b373da16a41b7d97 (patch) | |
| tree | 136965eee60884d6372ebf4bb9411e393b588653 | |
| parent | f9530009f698546b2269b268c4480b74b78de5dd (diff) | |
| download | qemu-2c0db8a985e7ee2740b16fc7b373da16a41b7d97.tar.gz qemu-2c0db8a985e7ee2740b16fc7b373da16a41b7d97.zip | |
target/riscv: Restore register dump zero padding
The register values lost their leading zeroes when the underlying type
was changed, resulting in mismatched padding and harder to read output.
Print with a runtime field width based on MXL, so values are 16 hex
digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids
adding target_ulong back into the dump.
Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20260813032421.54438-1-joel@jms.id.au>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 409c7d8682ae91c5e275d744d55a2ac19789534a)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | target/riscv/cpu.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 45b7610aa4..b04beee5cb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -650,6 +650,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + bool rv32 = riscv_cpu_is_32bit(cpu); + int width = rv32 ? 8 : 16; + uint64_t mask = rv32 ? UINT32_MAX : UINT64_MAX; int i, j; uint8_t *p; @@ -664,7 +667,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %-13s %d\n", "elp", env->elp); } #endif - qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc); + qemu_fprintf(f, " %-13s %0*" PRIx64 "\n", "pc", width, env->pc & mask); #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) for (i = 0; i < ARRAY_SIZE(csr_ops); i++) { int csrno = i; @@ -691,8 +694,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #endif for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %-8s %" PRIx64, - riscv_int_regnames[i], env->gpr[i]); + qemu_fprintf(f, " %-8s %0*" PRIx64, + riscv_int_regnames[i], width, env->gpr[i] & mask); if ((i & 3) == 3) { qemu_fprintf(f, "\n"); } |
