diff options
| author | wangyang <wangyang25@otcaix.iscas.ac.cn> | 2026-08-13 18:39:06 +0800 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2026-08-24 21:59:07 +0300 |
| commit | d1f63a04cf8e45ba3722348a3505e9ee2513750d (patch) | |
| tree | 43fa4a18c02785cd180222bbea71409d7c4b3291 | |
| parent | bb72fd7010921cba5f4eb6fec90009580060a8bd (diff) | |
| download | qemu-d1f63a04cf8e45ba3722348a3505e9ee2513750d.tar.gz qemu-d1f63a04cf8e45ba3722348a3505e9ee2513750d.zip | |
target/riscv: reject FMV.X.W/FMV.W.X under Zfinx
Zfinx explicitly excludes the FMV transfer instructions, but
trans_fmv_x_w/trans_fmv_w_x used REQUIRE_ZFINX_OR_F so a Zfinx-only
CPU accepted them. Require RVF instead so the transfers trap with
an illegal instruction when only Zfinx is present.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4108
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn>
Message-ID: <36c7cfebd27b4b6e8bcdd00e09e9dda0@wangyang25.otcaix.iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit af1e669cef162e8d9b5f2f176e8b909d61c4b530)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | target/riscv/tcg/insn_trans/trans_rvf.c.inc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc b/target/riscv/tcg/insn_trans/trans_rvf.c.inc index e935523c93..305f545b49 100644 --- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc @@ -428,7 +428,8 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a) { /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */ REQUIRE_FPU; - REQUIRE_ZFINX_OR_F(ctx); + /* Zfinx explicitly excludes the FMV transfer instructions. */ + REQUIRE_EXT(ctx, RVF); TCGv dest = dest_gpr(ctx, a->rd); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); @@ -531,7 +532,8 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) { /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */ REQUIRE_FPU; - REQUIRE_ZFINX_OR_F(ctx); + /* Zfinx explicitly excludes the FMV transfer instructions. */ + REQUIRE_EXT(ctx, RVF); TCGv_i64 dest = dest_fpr(ctx, a->rd); TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO); |