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| author | Boyan Karatotev <boyan.karatotev@arm.com> | 2026-09-07 16:08:00 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2026-09-07 16:08:00 +0000 |
| commit | 35cb6dabe9816d8c7b50e172e71ec3a81f1791e7 (patch) | |
| tree | 7f823b91a5a9452c54ca0260494fc72d90b12417 | |
| parent | 083e5cce0b4b26e229caef3632af4305a2928879 (diff) | |
| parent | bef5828426f9d6776384169aaecf3cc3a147ff78 (diff) | |
| download | arm-trusted-firmware-35cb6dabe9816d8c7b50e172e71ec3a81f1791e7.tar.gz arm-trusted-firmware-35cb6dabe9816d8c7b50e172e71ec3a81f1791e7.zip | |
Merge "fix(intel): remove F2S idle request after bridge disable" into integration
| -rw-r--r-- | plat/intel/soc/common/soc/socfpga_reset_manager.c | 31 |
1 files changed, 10 insertions, 21 deletions
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c index c9145e687..e461810fa 100644 --- a/plat/intel/soc/common/soc/socfpga_reset_manager.c +++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c @@ -836,35 +836,23 @@ int socfpga_bridges_enable(uint32_t mask) return ret; } -int socfpga_bridge_nongraceful_disable(uint32_t mask) +int socfpga_bridge_nongraceful_disable(uint32_t f2s_force_drain, + uint32_t f2s_respempty) { int ret = 0; - int timeout = 1000; - uint32_t brg_mask = 0; - uint32_t f2s_idlereq = 0; - uint32_t f2s_force_drain = 0; - uint32_t f2s_en = 0; - uint32_t f2s_idleack = 0; - uint32_t f2s_respempty = 0; - uint32_t f2s_cmdidle = 0; - - socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq, - &f2s_force_drain, &f2s_en, - &f2s_idleack, &f2s_respempty, &f2s_cmdidle); - - mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), - f2s_idlereq); + int timeout = 300; + uint32_t idle_status = 0; /* Time out Error - Bus is still active */ /* Performing a non-graceful shutdown with Force drain */ mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), f2s_force_drain); + udelay(5); ret = -ETIMEDOUT; - do { - /* Read response queue status to ensure it is empty */ - uint32_t idle_status; + /* Read response queue status to ensure it is empty */ + do { idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0)); if ((idle_status & f2s_respempty) != 0U) { idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0)); @@ -875,7 +863,7 @@ int socfpga_bridge_nongraceful_disable(uint32_t mask) } } - asm("nop"); + udelay(1000); } while (timeout-- > 0); @@ -1188,7 +1176,8 @@ int socfpga_bridges_disable(uint32_t mask) f2s_en); udelay(5); - ret = socfpga_bridge_nongraceful_disable(mask); + ret = socfpga_bridge_nongraceful_disable(f2s_force_drain, + f2s_respempty); /* Bridge reset */ #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 |