Merge changes from topic "nbxv3-rcw-stamp" into integration

* changes:
  docs(nbxv3): fix DDR FIP build instructions
  feat(nbxv3): print the RCW build stamp from BL2

1 files changed, 40 insertions, 1 deletions

diff --git a/docs/plat/nxp/nbxv3.rst b/docs/plat/nxp/nbxv3.rst
index 44d65faf2..d0e977fda 100644
--- a/docs/plat/nxp/nbxv3.rst
+++ b/docs/plat/nxp/nbxv3.rst
@@ -87,6 +87,38 @@ U-Boot + kernel + ramdisk. Smaller manifests provision faster over the
 JTAG semihosting link. The schema is documented in
 ``plat/nxp/soc-lx2160a/nbxv3/MANIFEST.md``.
 
+RCW build stamp (PBL -> BL2)
+----------------------------
+
+The RCW carries no version which prevents the software identification.
+On this board, this identification is set into one of the LX2160A DCFG
+general-purpose scratch registers, ``SCRATCHRW13``.
+
+The PBI command block embedded in the PBL writes it while the boot
+Service Processor processes the RCW, and the DCFG
+``SCRATCHRW`` registers survive the hand-off to BL2 (they are cleared
+only by a power-on reset).
+
+The 32-bit word is packed, all-BCD::
+
+    31   28 27   24 23   16 15    8 7     0
+   +-------+-------+-------+-------+-------+
+   |CARRIER|  TAG  |  YY   |  MM   |  DD   |   all BCD
+   +-------+-------+-------+-------+-------+
+
+- **CARRIER** identifies the carrier board the CPU module is plugged into.
+- **TAG** is a fixed marker, ``0xB``
+- **YY / MM / DD** are the RCW build date in BCD
+
+The first boot lines based on the RCW shall be some of the following::
+
+     NOTICE  Iliad nbxv32 RCW v.20260820
+     NOTICE  Iliad nbxv3 (bring-up, no IO) RCW v.20260820
+
+This pairs with the ``MEM_PLL_RAT`` probe: that register tells BL2
+*whether* a production RCW is live, while ``SCRATCHRW13`` tells it
+*which* one, and on *which* carrier.
+
 Board policy deviations from the LX2160A reference boards
 ---------------------------------------------------------
 
@@ -106,12 +138,19 @@ Board policy deviations from the LX2160A reference boards
 Building
 --------
 
+The ``fip_ddr`` target packs the Synopsys DDR PHY training firmware.
+Get it using a NXP clone of ``ddr-phy-binary`` repository into the TF-A
+root so the default ``DDR_PHY_BIN_PATH`` (``./ddr-phy-binary/lx2160a``)
+resolves::
+
+    git clone https://github.com/NXP/ddr-phy-binary
+
 Production XIP BL2 + FIP (embedded in the PBL at NOR offset 0x9000):
 
 .. code:: shell
 
     make PLAT=nbxv3 BOOT_MODE=flexspi_nor RCW=$RCW_BIN BL33=$UBOOT_BIN \
-         pbl fip fip-ddr
+         pbl fip fip_ddr
 
 Bootstrap BL2 (build, loaded by OpenOCD into OCRAM, resolves staged
 images over ARM semihosting):