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| author | Scaria Kochidanadu <s-kochidanadu@ti.com> | 2026-07-31 14:23:41 +0530 |
|---|---|---|
| committer | Scaria Kochidanadu <s-kochidanadu@ti.com> | 2026-07-31 14:23:41 +0530 |
| commit | e0efbaa8db03444f1c4641c9bd72884e552376b0 (patch) | |
| tree | fb80e83cccafd15f2903735c1d15d4843ac3cc10 /drivers | |
| parent | 92d930f35917c39042b8cf43423c695cc2e2589a (diff) | |
| download | arm-trusted-firmware-e0efbaa8db03444f1c4641c9bd72884e552376b0.tar.gz arm-trusted-firmware-e0efbaa8db03444f1c4641c9bd72884e552376b0.zip | |
fix(ti/clk): fix false success in ti_clk_div_set_freq_static_parent
ti_clk_div_set_freq_static_parent() searches two candidate dividers:
div0 = floor(parent_freq / target_hz) and div1 = div0 + 1.
The div1 range check only tests the lower bound (div1_hz >= min_hz) with
no upper bound check. When the ideal divider exceeds max_div, div0 is
clamped to max_div - 1 and div1 = max_div. Both candidates now produce
a frequency above the target. The missing upper bound on div1 causes
div1_hz > target_hz to pass the check when called with min_hz = max_hz =
target_hz, making the function return a false success. The caller in
clk_pll_16fft_hsdiv_set_freq then exits early without reprogramming the
PLL VCO to reach the requested frequency.
Add the missing div1_hz <= max_hz check. The lower bound check on div0
is not needed since div0 is the floor divider, guaranteeing div0_hz >=
target_hz >= min_hz by construction.
Change-Id: If323887df5e31e8d4e41600530222cfabd3652cd
Signed-off-by: Scaria Kochidanadu <s-kochidanadu@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ti/clk/ti_clk_div.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ti/clk/ti_clk_div.c b/drivers/ti/clk/ti_clk_div.c index 2884a1847..12e59d5f6 100644 --- a/drivers/ti/clk/ti_clk_div.c +++ b/drivers/ti/clk/ti_clk_div.c @@ -253,7 +253,7 @@ uint32_t ti_clk_div_set_freq_static_parent(struct ti_clk *clkp, uint32_t target_ div1_hz = 0U; if (div1 <= n) { div1_hz = parent_freq_hz / div1; - if (div1_hz >= min_hz) { + if ((div1_hz >= min_hz) && (div1_hz <= max_hz)) { div1_ok = true; div1_delta = target_hz - div1_hz; } else { |