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| author | Nicolas Le Bayon <nicolas.le.bayon@st.com> | 2023-09-30 17:47:08 +0200 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@st.com> | 2026-02-05 09:16:49 +0100 |
| commit | e0a6bfe87f84f505d8b26432d2405015cc77c329 (patch) | |
| tree | 60a4ae5d65c510d8439a8789f924273c9d343ee7 /fdts | |
| parent | f262ebf61dd0072baaca63687f11ae53fef413bd (diff) | |
| download | arm-trusted-firmware-e0a6bfe87f84f505d8b26432d2405015cc77c329.tar.gz arm-trusted-firmware-e0a6bfe87f84f505d8b26432d2405015cc77c329.zip | |
feat(stm32mp21): manage STM32MP21 DT overlays
Add BL2 and BL31 DT overlays for STM32MP21 and their management in
platform.mk file.
Change-Id: I6ea0861280befa6b4f20c7cd7feef97cbdb7a0ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/stm32mp21-bl2.dtsi | 74 | ||||
| -rw-r--r-- | fdts/stm32mp21-bl31.dtsi | 16 |
2 files changed, 90 insertions, 0 deletions
diff --git a/fdts/stm32mp21-bl2.dtsi b/fdts/stm32mp21-bl2.dtsi new file mode 100644 index 000000000..ccc79cb13 --- /dev/null +++ b/fdts/stm32mp21-bl2.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2026, STMicroelectronics - All Rights Reserved + */ + +#include <platform_def.h> + +/ { + soc@0 { +#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR + bus@42080000 { + /delete-node/ spi@40430000; + }; +#endif +#if !STM32MP_RAW_NAND + /delete-node/ memory-controller@48200000; +#endif +#if !STM32MP_EMMC && !STM32MP_SDMMC + bus@42080000 { + /delete-node/ mmc@48220000; + /delete-node/ mmc@48230000; + }; +#endif + }; + + /* + * UUID's here are UUID RFC 4122 compliant meaning fieds are stored in + * network order (big endian) + */ + + st-io_policies { + fip-handles { + compatible = "st,io-fip-handle"; +#if STM32MP_DDR_FIP_IO_STORAGE + ddr_fw_uuid = "b11249be-92dd-4b10-867c-2c6a4b47a7fb"; +#endif + fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e"; + bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00"; + bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38"; + bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288"; + bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9"; + bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4"; + hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc"; + soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0"; + tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; + nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; +#if TRUSTED_BOARD_BOOT + stm32mp_cfg_cert_uuid = "501d8dd2-8bce-49a5-84eb-559a9f2eaeaf"; + t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c"; + soc_fw_key_uuid = "8ab8becc-f960-e411-9ad0-eb4822d8dcf8"; + tos_fw_key_cert_uuid = "9477d603-fb60-e411-85dd-b7105b8cee04"; + nt_fw_key_cert_uuid = "8ad5832a-fb60-e411-8aaf-df30bbc49859"; + soc_fw_content_cert_uuid = "e2b20c20-5e63-e411-9ce8-abccf92bb666"; + tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d"; + nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7"; +#endif + }; + }; + +#if TRUSTED_BOARD_BOOT + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + mbedtls_heap_addr = <0x0 STM32MP_MBEDTLS_HEAP_BASE>; + mbedtls_heap_size = <STM32MP_MBEDTLS_HEAP_SIZE>; + }; + +#include "stm32mp2-cot-descriptors.dtsi" +#endif + +}; diff --git a/fdts/stm32mp21-bl31.dtsi b/fdts/stm32mp21-bl31.dtsi new file mode 100644 index 000000000..7ce10f8a8 --- /dev/null +++ b/fdts/stm32mp21-bl31.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2026, STMicroelectronics - All Rights Reserved + */ + +/ { + soc@0 { + /delete-node/ memory-controller@48200000; + + bus@42080000 { + /delete-node/ spi@40430000; + /delete-node/ mmc@48220000; + /delete-node/ mmc@48230000; + }; + }; +}; |