Merge changes from topic "arm-support-l1l2-core-pd" into integration

* changes:
  feat(arm): support PSCI idle states for platforms with 2 core PDs
  feat(dsu): support new L2Core PD PPU states

3 files changed, 52 insertions, 7 deletions

diff --git a/include/drivers/arm/dsu.h b/include/drivers/arm/dsu.h
index c6a8b4a3f..3dcb2e4f9 100644
--- a/include/drivers/arm/dsu.h
+++ b/include/drivers/arm/dsu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2025-2026, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -62,5 +62,12 @@ void cluster_on_dsu_pmu_context_restore(void);
 void cluster_off_dsu_pmu_context_save(void);
 
 void dsu_driver_init(const dsu_driver_data_t *data);
+
+#if DSU_PDL2_SUPPORT
+void dsu_configure_core_l2pd_power_required(bool power_required);
+void dsu_configure_core_wfi_logicret_ctrl(unsigned int logicret_ctrl);
+void dsu_configure_core_wfi_fullret_ctrl(unsigned int fullret_ctrl);
+#endif /* DSU_PDL2_SUPPORT */
+
 #endif
 #endif /* DSU_H */
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index 089ea5240..64d882bf8 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2026, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -53,6 +53,24 @@
 #define CLUSTERPWRDN_MEMRET_WIDTH	U(1)
 #define CLUSTERPWRDN_MEMRET_SHIFT	U(1)
 
+#if DSU_PDL2_SUPPORT
+/* L2PDPWRCTLR_EL1 register definitions */
+#define L2PDPWRCTLR_EL1			S3_0_C15_C7_1
+#define L2PDPWRCTLR_EL1_NOL2PWRDN_WIDTH	U(1)
+#define L2PDPWRCTLR_EL1_NOL2PWRDN_SHIFT	U(0)
+
+DEFINE_RENAME_SYSREG_RW_FUNCS(l2pdpwrctlr_el1, L2PDPWRCTLR_EL1)
+
+/* CPUPWRCTLR_EL1 register definitions */
+#define CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CPUPWRCTLR_EL1_WFI_FULLRET_CTRL_WIDTH	U(3)
+#define CPUPWRCTLR_EL1_WFI_FULLRET_CTRL_SHIFT	U(4)
+#define CPUPWRCTLR_EL1_WFI_LOGICRET_CTRL_WIDTH	U(3)
+#define CPUPWRCTLR_EL1_WFI_LOGICRET_CTRL_SHIFT	U(13)
+
+DEFINE_RENAME_SYSREG_RW_FUNCS(cpupwrctlr_el1, CPUPWRCTLR_EL1)
+#endif
+
 /********************************************************************
  * Masks applied for DSU errata workarounds
  ********************************************************************/
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index f1828f094..8fbc764a8 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -41,12 +41,32 @@
  *  within the power-state parameter.
  */
 /* Local power state for power domains in Run state. */
-#define ARM_LOCAL_STATE_RUN	U(0)
+#define ARM_LOCAL_STATE_RUN		U(0)
 /* Local power state for retention. Valid only for CPU power domains */
-#define ARM_LOCAL_STATE_RET	U(1)
-/* Local power state for OFF/power-down. Valid for CPU and cluster power
-   domains */
-#define ARM_LOCAL_STATE_OFF	U(2)
+
+
+/* Define the minimum and maximum off and retention states for PDs.
+ * MIN_OFF may only be valid for certain PDs, OFF is valid for all PDs.
+ */
+#if DSU_PDL2_SUPPORT
+
+/* Retention states are valid only for CPU power domains. */
+#define ARM_LOCAL_STATE_RETL1		U(1)
+#define ARM_LOCAL_STATE_MIN_RET		ARM_LOCAL_STATE_RETL1
+#define ARM_LOCAL_STATE_RET		U(2)
+
+#define ARM_LOCAL_STATE_OFFL1		U(3)
+#define ARM_LOCAL_STATE_MIN_OFF		ARM_LOCAL_STATE_OFFL1
+#define ARM_LOCAL_STATE_OFF		U(4)
+#else
+
+/* Retention states are valid only for CPU power domains. */
+#define ARM_LOCAL_STATE_MIN_RET		U(1)
+#define ARM_LOCAL_STATE_RET		U(1)
+
+#define ARM_LOCAL_STATE_MIN_OFF		U(2)
+#define ARM_LOCAL_STATE_OFF		U(2)
+#endif
 
 /* Memory location options for TSP */
 #define ARM_TRUSTED_SRAM_ID		0