diff options
| author | Bryan Chan Jia Ching <bryan.chan@altera.com> | 2026-04-23 00:00:00 +0800 |
|---|---|---|
| committer | Jit Loon Lim <jit.loon.lim@altera.com> | 2026-09-02 19:36:44 +0800 |
| commit | 8ebc0d650c772351d936520a9bdf040935e4844b (patch) | |
| tree | dcc856f3811abd75dda4307483506e74bb5c2fd9 /include | |
| parent | 4ea4097af03021ffef1f60697e6002efb465a37e (diff) | |
| download | arm-trusted-firmware-8ebc0d650c772351d936520a9bdf040935e4844b.tar.gz arm-trusted-firmware-8ebc0d650c772351d936520a9bdf040935e4844b.zip | |
fix(cadence): use device-specific SDMMC default clocks
SD cards and eMMC devices have different safe default clock rates. The
Cadence driver used the same rate for both protocols and also selected
an incorrect bus voltage during card reset.
Use 50 MHz for high-speed SD cards and the 26 MHz legacy rate for eMMC.
Select the reset voltage according to the device type and consolidate
the clock setup in the SDMMC driver.
Change-Id: I6d2f5ed9d1df8661cd39076f77bca8d01387df5f
Signed-off-by: Bryan Chan Jia Ching <bryan.chan@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/cadence/cdns_combo_phy.h | 1 | ||||
| -rw-r--r-- | include/drivers/cadence/cdns_sdmmc.h | 10 |
2 files changed, 8 insertions, 3 deletions
diff --git a/include/drivers/cadence/cdns_combo_phy.h b/include/drivers/cadence/cdns_combo_phy.h index 4d3a75394..8dddbee16 100644 --- a/include/drivers/cadence/cdns_combo_phy.h +++ b/include/drivers/cadence/cdns_combo_phy.h @@ -234,6 +234,5 @@ struct cdns_sdmmc_combo_phy { int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, uint32_t phy_reg_data, uint32_t phy_reg_data_value); int cdns_sd_card_detect(void); -int cdns_emmc_card_reset(void); #endif
\ No newline at end of file diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h index f4485ca8d..4f4fd7b0e 100644 --- a/include/drivers/cadence/cdns_sdmmc.h +++ b/include/drivers/cadence/cdns_sdmmc.h @@ -446,10 +446,16 @@ #define CONFIG_CDNS_DESC_COUNT 8 /* - * To accommodate SDMCLK set to 200MHz - * TODO: To support various clock range + * SD card, according to SD Host Controller Simplified Specification + * will be using High Speed default 50MHz as we have enabled HS mode. + * eMMC, according to JEDEC JESD84-B51, will be using legacy default + * 26MHz for max compatibility. */ +#if MMC_DEVICE_TYPE == 1 #define SDEMMC_SDCLK 50000000U +#else +#define SDEMMC_SDCLK 26000000U +#endif enum sd_opcode { SD_GO_IDLE_STATE = 0, |