Merge changes I6ca4b63c,I69e7ead3,I00b76de0 into integration

* changes:
  fix(cpus): add workaround for C1-Nano erratum 4497400
  fix(cpus): add workaround for Cortex-A520 erratum 4491980
  fix(cpus): add workaround for Cortex-A510 erratum 4568615

6 files changed, 106 insertions, 0 deletions

diff --git a/lib/cpus/aarch64/c1_nano.S b/lib/cpus/aarch64/c1_nano.S
index ccc7786bc..ad2ff49e2 100644
--- a/lib/cpus/aarch64/c1_nano.S
+++ b/lib/cpus/aarch64/c1_nano.S
@@ -112,6 +112,36 @@ workaround_runtime_end c1_nano, ERRATUM(3754876)
 
 check_erratum_ls c1_nano, ERRATUM(3754876), CPU_REV(0, 1)
 
+	.pushsection .data
+	.align	4
+safe_info:
+	.quad	0x1122334455667788
+	.quad	0x1122334455667788
+	.popsection
+
+.global erratum_c1_nano_4497400_wa
+workaround_runtime_start c1_nano, ERRATUM(4497400), ERRATA_C1NANO_4497400
+	adr_l	x1, safe_info
+	mov	x0, #4
+	.balign	16
+1:
+	sb_barrier_insn
+	ldp	x2, x3, [x1, #0]
+	ldp	x2, x3, [x1, #0]
+	subs	x0, x0, #1
+	sb_barrier_insn
+	nop
+	ldp	x2, x3, [x1, #0]
+	ldp	x2, x3, [x1, #0]
+	sb_barrier_insn
+	ldp	x2, x3, [x1, #0]
+	ldp	x2, x3, [x1, #0]
+	b.ne	1b
+	sb_barrier_insn
+workaround_runtime_end c1_nano, ERRATUM(4497400), NO_ISB
+
+check_erratum_ls c1_nano, ERRATUM(4497400), CPU_REV(0, 2)
+
 cpu_reset_func_start c1_nano
 	/* ----------------------------------------------------
 	 * Disable speculative loads
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 0747ac323..97ce5c5fd 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -312,6 +312,27 @@ workaround_reset_end cortex_a510, ERRATUM(3704847)
 
 check_erratum_ls cortex_a510, ERRATUM(3704847), CPU_REV(1, 3)
 
+.global erratum_cortex_a510_4568615_wa
+workaround_runtime_start cortex_a510, ERRATUM(4568615), ERRATA_A510_4568615
+	/*
+	 * the workaround is expected to be called with sp_el3 which points to a
+	 * context structure. Switch to sp_el0 to use dynamically
+	 */
+	mrs	x0, spsel
+	msr	spsel, #MODE_SP_EL0
+
+	/* in order to not affect context, push two Q registers to the stack */
+	stp	q0, q1, [sp, #-32]
+	/* use the lower EL Q registers to perfom the workaround */
+	ldp	q0, q1, [sp, #-32]
+	ldp	q0, q1, [sp, #-32]
+	ldp	q0, q1, [sp, #-32]
+
+	msr	spsel, x0
+workaround_runtime_end cortex_a510, ERRATUM(4568615), NO_ISB
+
+check_erratum_chosen cortex_a510, ERRATUM(4568615), ERRATA_A510_4568615
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index e94c7104f..6cd5bca58 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -93,6 +93,28 @@ workaround_reset_end cortex_a520, ERRATUM(3685825)
 
 check_erratum_chosen cortex_a520, ERRATUM(3685825), ERRATA_A520_3685825
 
+.global erratum_cortex_a520_4491980_wa
+workaround_runtime_start cortex_a520, ERRATUM(4491980), ERRATA_A520_4491980
+	/*
+	 * the workaround is expected to be called with sp_el3 which points to a
+	 * context structure. Switch to sp_el0 to use dynamically
+	 */
+	mrs	x0, spsel
+	msr	spsel, #MODE_SP_EL0
+
+	/* in order to not affect context, push two Q registers to the stack */
+	stp	q0, q1, [sp, #-32]
+	/* use the lower EL Q registers to perfom the workaround */
+	ldp	q0, q1, [sp, #-32]
+	ldp	q0, q1, [sp, #-32]
+	ldp	q0, q1, [sp, #-32]
+
+	msr	spsel, x0
+workaround_runtime_end cortex_a520, ERRATUM(4491980), NO_ISB
+
+check_erratum_chosen cortex_a520, ERRATUM(4491980), ERRATA_A520_4491980
+
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index d05ad8fd3..511008439 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -408,12 +408,14 @@ CPU_FLAG_LIST += ERRATA_A510_2684597
 CPU_FLAG_LIST += ERRATA_A510_2971420
 CPU_FLAG_LIST += ERRATA_A510_3672349
 CPU_FLAG_LIST += ERRATA_A510_3704847
+CPU_FLAG_LIST += ERRATA_A510_4568615
 CPU_FLAG_LIST += ERRATA_A520_2630792
 CPU_FLAG_LIST += ERRATA_A520_2677201
 CPU_FLAG_LIST += ERRATA_A520_2858100
 CPU_FLAG_LIST += ERRATA_A520_2938996
 CPU_FLAG_LIST += ERRATA_A520_3631357
 CPU_FLAG_LIST += ERRATA_A520_3685825
+CPU_FLAG_LIST += ERRATA_A520_4491980
 CPU_FLAG_LIST += ERRATA_V2_2394277
 CPU_FLAG_LIST += ERRATA_V2_2618597
 CPU_FLAG_LIST += ERRATA_V2_2662553
@@ -494,6 +496,7 @@ CPU_FLAG_LIST += ERRATA_C1NANO_3516455
 CPU_FLAG_LIST += ERRATA_C1NANO_3616450
 CPU_FLAG_LIST += ERRATA_C1NANO_3630925
 CPU_FLAG_LIST += ERRATA_C1NANO_3754876
+CPU_FLAG_LIST += ERRATA_C1NANO_4497400
 CPU_FLAG_LIST += ERRATA_DSU_798953
 CPU_FLAG_LIST += ERRATA_DSU_936184
 CPU_FLAG_LIST += ERRATA_DSU_2313941
diff --git a/lib/cpus/errata_common_asm.S b/lib/cpus/errata_common_asm.S
new file mode 100644
index 000000000..a669cd885
--- /dev/null
+++ b/lib/cpus/errata_common_asm.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2026, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <cortex_a510.h>
+#include <cortex_a520.h>
+#include <c1_nano.h>
+
+
+.global apply_faulting_side_channel_wa
+func apply_faulting_side_channel_wa
+	jump_if_not_cpu_midr	CORTEX_A510_MIDR, a520
+	apply_erratum	cortex_a510, ERRATUM(4568615), ERRATA_A510_4568615
+a520:
+	jump_if_not_cpu_midr	CORTEX_A520_MIDR, c1_nano
+	apply_erratum	cortex_a520, ERRATUM(4491980), ERRATA_A520_4491980, NO_GET_CPU_REV
+c1_nano:
+	jump_if_not_cpu_midr	C1_NANO_MIDR, end_wa
+	apply_erratum	c1_nano, ERRATUM(4497400), ERRATA_C1NANO_4497400, NO_GET_CPU_REV
+end_wa:
+ret
+endfunc apply_faulting_side_channel_wa
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index e9438bad6..564dcf44a 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -684,6 +684,10 @@ no_mpam:
 
 	restore_ptw_el1_sys_regs
 
+#if IMAGE_BL31 && (ERRATA_A510_4568615 || ERRATA_A520_4491980 || ERRATA_C1NANO_4497400)
+	bl	apply_faulting_side_channel_wa
+#endif /* IMAGE_BL31 && (ERRATA_A510_4568615 || ERRATA_A520_4491980 || ERRATA_C1NANO_4497400) */
+
 	/* ----------------------------------------------------------
 	 * Restore general purpose (including x30), PMCR_EL0 and
 	 * ARMv8.3-PAuth registers.