Merge changes I668505c9,I5e1f8fbd,I1692ddc7,I41663884,I81e6f73e, ... into integration

* changes:
  fix(docs): don't say FEAT_AMU isn't contexted
  docs(cpufeat): add a note about PSTATE bits and new features
  feat(docs): add commit message guidelines for new feature additions
  refactor(cpufeat): move FEAT_TRBE constraints to constraints.mk
  fix(cpufeat): remove FEAT_SEBEP
  refactor(cpufeat): always use is_feat_abc_supported()
  fix(el3-runtime): add the target EL check for PSTATE.EXLOCK

7 files changed, 13 insertions, 14 deletions

diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 942f7d2dd..5b3ae40e0 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -149,7 +149,7 @@ static void enable_extensions_nonsecure(bool el2_unused)
 		trf_init_el3();
 	}
 
-	if (is_feat_pmuv3_present()) {
+	if (is_feat_pmuv3_supported()) {
 		pmuv3_init_el3();
 	}
 #endif /*  IMAGE_BL32 */
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 96c7c7e4a..cd289fd90 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -978,7 +978,6 @@ void cm_init_percpu_once_regs(void)
 static void manage_extensions_nonsecure(cpu_context_t *ctx)
 {
 #ifdef IMAGE_BL31
-	/* NOTE: registers are not context switched */
 	if (is_feat_amu_supported()) {
 		amu_enable(ctx);
 	}
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index bd5ad319f..2c77d02a9 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2026, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -48,7 +48,7 @@ void sme_init_el3(void)
 	 * using SMCR_EL2 and SMCR_EL1.
 	 */
 	smcr_el3 = SMCR_ELX_LEN_MAX;
-	if (is_feat_sme_fa64_present()) {
+	if (is_feat_sme_fa64_supported()) {
 		VERBOSE("[SME] FA64 enabled\n");
 		smcr_el3 |= SMCR_ELX_FA64_BIT;
 	}
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index b887497cb..561877491 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -337,7 +337,7 @@ static bool is_gpi_valid(unsigned int gpi)
 	case GPT_GPI_ANY:
 		return true;
 	case GPT_GPI_NSO:
-		return is_feat_rme_gpc2_present();
+		return is_feat_rme_gpc2_supported();
 	case GPT_GPI_SA:
 	case GPT_GPI_NSP:
 		return is_feat_rme_gdi_supported();
@@ -1156,7 +1156,7 @@ int gpt_enable(void)
 	gpccr_el3 |= GPCCR_GPC_BIT;
 
 	/* Enable NSO encoding if FEAT_RME_GPC2 is supported. */
-	if (is_feat_rme_gpc2_present()) {
+	if (is_feat_rme_gpc2_supported()) {
 		gpccr_el3 |= GPCCR_NSO_BIT;
 
 		/* Enable NSO in NS transition policies. */
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index 36cfbd313..0fe653f6e 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -86,7 +86,7 @@ static uintptr_t xlat_get_min_virt_addr_space_size(void)
 {
 	uintptr_t ret;
 
-	if (is_feat_ttst_present())
+	if (is_feat_ttst_supported())
 		ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
 	else
 		ret = MIN_VIRT_ADDR_SPACE_SIZE;
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index 6817b504a..ff73a88a2 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -250,7 +250,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags,
 	/* Set TTBR0 bits as well */
 	ttbr0 = (uint64_t)(uintptr_t) base_table;
 
-	if (is_feat_ttcnp_present()) {
+	if (is_feat_ttcnp_supported()) {
 		/* Enable CnP bit so as to share page tables with all PEs. */
 		ttbr0 |= TTBR_CNP_BIT;
 	}
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index 08c89b65d..4539b0292 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -25,12 +25,12 @@ bool xlat_arch_is_granule_size_supported(size_t size)
 {
 	if (size == PAGE_SIZE_4KB) {
 		/* MSB of TGRAN4 field will be '1' for unsupported feature */
-		return is_feat_tgran4K_present();
+		return is_feat_tgran4K_supported();
 	} else if (size == PAGE_SIZE_16KB) {
-		return is_feat_tgran16K_present();
+		return is_feat_tgran16K_supported();
 	} else if (size == PAGE_SIZE_64KB) {
 		/* MSB of TGRAN64 field will be '1' for unsupported feature */
-		return is_feat_tgran64K_present();
+		return is_feat_tgran64K_supported();
 	} else {
 		return false;
 	}
@@ -181,7 +181,7 @@ uintptr_t xlat_get_min_virt_addr_space_size(void)
 {
 	uintptr_t ret;
 
-	if (is_feat_ttst_present())
+	if (is_feat_ttst_supported())
 		ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
 	else
 		ret = MIN_VIRT_ADDR_SPACE_SIZE;
@@ -371,7 +371,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags,
 	/* Set TTBR bits as well */
 	ttbr0 = (uint64_t) base_table;
 
-	if (is_feat_ttcnp_present()) {
+	if (is_feat_ttcnp_supported()) {
 		/* Enable CnP bit so as to share page tables with all PEs. */
 		ttbr0 |= TTBR_CNP_BIT;
 	}