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-rw-r--r--include/drivers/cadence/cdns_combo_phy.h1
-rw-r--r--include/drivers/cadence/cdns_sdmmc.h12
2 files changed, 10 insertions, 3 deletions
diff --git a/include/drivers/cadence/cdns_combo_phy.h b/include/drivers/cadence/cdns_combo_phy.h
index 4d3a75394..8dddbee16 100644
--- a/include/drivers/cadence/cdns_combo_phy.h
+++ b/include/drivers/cadence/cdns_combo_phy.h
@@ -234,6 +234,5 @@ struct cdns_sdmmc_combo_phy {
int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value,
uint32_t phy_reg_data, uint32_t phy_reg_data_value);
int cdns_sd_card_detect(void);
-int cdns_emmc_card_reset(void);
#endif \ No newline at end of file
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index f4485ca8d..69ee5a1c9 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -12,6 +12,8 @@
#include <drivers/cadence/cdns_combo_phy.h>
#include <drivers/mmc.h>
+#include <platform_def.h>
+
#if MMC_DEVICE_TYPE == 0
#define CONFIG_DMA_ADDR_T_64BIT 0
#endif
@@ -446,10 +448,16 @@
#define CONFIG_CDNS_DESC_COUNT 8
/*
- * To accommodate SDMCLK set to 200MHz
- * TODO: To support various clock range
+ * SD card, according to SD Host Controller Simplified Specification
+ * will be using High Speed default 50MHz as we have enabled HS mode.
+ * eMMC, according to JEDEC JESD84-B51, will be using legacy default
+ * 26MHz for max compatibility.
*/
+#if MMC_DEVICE_TYPE == 1
#define SDEMMC_SDCLK 50000000U
+#else
+#define SDEMMC_SDCLK 26000000U
+#endif
enum sd_opcode {
SD_GO_IDLE_STATE = 0,