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This allows a dedicated build, and avoid BL_FLAGS compilation flags.
The code size does not increase, it has been checked on ST platforms:
STM32MP13 and STM32MP25.
Change-Id: I5ff3c40222770400a97dd4d451aeebc26fef4f2a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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For platforms not including bl31.mk, especially Armv7/aarch32 platforms,
The flags FIRME_SUPPORT and FIRME_SUPPORT_IDE_KM will not be defined (to
0), which causes a build warning, as FIRME_SUPPORT_IDE_KM is used in a
common file (include/plat/common/platform.h). The behavior does not
change as the default values for those flags are 0 (in default.mk).
Change-Id: Ibce324db896943e249220246bb41d4fb34af8d02
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Execute expressions directly without `eval` when they do not expand to
Make syntax (i.e. where `eval` is provably pointless).
Additionally, remove the obsolete `eval` feature check - we mandate at
least GNU Make 4.3, which always supports it.
Change-Id: I26f1723f084d0428a2cbe336e76f0765a9818a5a
Signed-off-by: Chris Kay <chris.kay@arm.com>
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Some TF-A platform build options are assigned unconditionally in common
files like arm_common.mk and Makefile. This required platforms to use
the GNU Make override keyword if a different value was desired.
This also had the effect of causing values supplied from the command
line to be ignored.
This commit changes the common defaults for select build options to use
a conditional assignment:
- ARM_PLAT_MT
- NEED_BL1
- NEED_BL2
- NEED_BL2U
- NEED_BL31
Also removes now-unnecessary overrides from the TC platform.mk.
Change-Id: Ia6c5ebc59ed95341424de376b470581c15603b9b
Signed-off-by: Alcaeus Lam <alcaeus.lam@arm.com>
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This adds on top of previous work for encryption support in the
encrypt_fw tool. It introduces the support for having
`DECRYPTION_SUPPORT=aes_ccm` in the build system and image decryption
in runtime.
Change-Id: Ia93c87265b1d8a2ceceeeafc7780d4032a09b6b8
Signed-off-by: Cesar Pastorini <cesar.pastorini@arm.com>
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FEAT_TRBE_EXC adds support for reporting trace buffer management events
as TRBE profiling exceptions.
This feature can be found in the M.a version of the Arm ARM.
Change-Id: I148dacfb6445e769820dd265a7d64e3b8c6e8ca2
Signed-off-by: Johann Scott <johann.scott@arm.com>
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FEAT_SRMASK adds a series of aliases and bitwise write masks for
some EL1 controls registers. The purpose of this is to reduce
trapping of EL1 system register accesses to EL2.
This feature can be found in the M.a version of the Arm ARM.
Change-Id: I15e26c4570da070562dec990cc3bacde240d4ad5
Signed-off-by: Johann Scott <johann.scott@arm.com>
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This is the first patch in the series to enable live firmware
activation in BL31, and it adds the build flag to enable this to
the makefiles.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0b6f511e61f9cdcc8ee786507ee1c2e721147da7
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The flag SMC_PCI_SUPPORT is set to 0 in make_helpers/defaults.mk. It can
then be defined in Makefile.
This will avoid warning for platforms not using SMC_PCI_SUPPORT with
-Wundef.
Change-Id: I142fd03ce3f01d098a2af93f63e7a3c322c71bdd
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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USE_GIC_DRIVER is defined as 0 in make_helpers/defaults.mk.
For platforms not overriding this default parameter, the flag will then
not be defined and will trigger warning when enabling -Wundef flag.
Move the flag in the call add_defines in Makefile. While at it, add it
also in call assert_numerics.
Change-Id: I2d1ea9193e32ea004ed7f78fa51fa63a0da55f35
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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SDEI_SUPPORT is set to 0 in make_helpers/defaults.mk, and can be set to
1 in platforms mk files. Its management with assert_booleans and
add_defines macros can then be done in Makfile.
For Aarch32 platforms, the bl31.mk file is not included, and the flag
is then not defined. It triggers warning when enabling -Wundef flag.
Change-Id: Icc034d711d70ae30e0ad78d177c8180d15f06d97
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Add support for Branch Record Buffer Extension v1.1. FEAT_BRBEv1p1
introduces MDCR_EL3.{E3BREW, E3BREC} which allow for branch recording at
EL3. This patch introduces helpers to start and stop recording as well
as dumping the branch record buffer to the console.
The helpers make sure that starting and stopping branch recording saves
and restores the lower EL BRBE context. This should help prevent
security and BRBE inconsistency issues if an actual payload is running
along side this. As this is a debug feature, no calls are expected to be
committed to the repository.
Note that this feature is marked as experimental. That is because
firmware does not need to support FEAT_BRBEv1p1 for the system to be
fully functional. As such, this flag may be renamed or removed in future
iterations once a precise usage model is arrived at.
Change-Id: Ibf2f1a5e9d36f759d7b381f06103d39debe23428
Co-developed-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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FEAT_AxERR provide controls for relaxing when External Aborts need to be
reported synchronously. Currently cores implement both features
together, so add a single shared flag for both. The feature is only
enabled at EL3 as lower ELs have their own ungraded controls.
These features can be found in the M.a version of the Arm ARM.
Change-Id: Id70c353000bbdb3a625aaa1cf09f6290fe201a42
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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This patch adds support via the FEAT_SPEv1p5 feature. Architecturally,
FEAT_SPEv1p5, FEAT_SPE_EXC, and FEAT_SPE_nVM are closely connected and
real implementations are expected with all three present. To simplifly a
little, only a flag for FEAT_SPEv1p5 is added. The underlying ID
registers for each respective feature are still checked so if a core
pops up that breaks the above assumption FEATURE_DETECTION should catch
it.
These features can be found in the M.a version of the Arm ARM.
Change-Id: I44ed3850f247dbfc8fd53fb735882887d0a008dd
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.15.0
Change-Id: I1cf5e657e0b7091e485506323bc483948f559be3
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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Architecturally, FEAT_CSV2_2 is an optional feature from Armv8.0 with
its only dependency being FEAT_CSV2 (mandatory from Armv8.5). There is
no architectural relation with ENABLE_RMM or FEAT_RME so this enable is
inappropriate.
Since its original introduction with 01cf14dd4, FEAT_CSV2_2 has become
feat_state aware and enabled by default on dynamic platfroms (fvp and
qemu). As such, in the unlikely event this enable serves a purpose, it
is duplicate to those.
Change-Id: I1c20eeeee1f4dda8c98bdfdc37b26be516f5ceba
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME related support is now enabled using feature detection option
ENABLE_FEAT_RME, this patch moves GPT support under ENABLE_FEAT_RME.
This change brings in below benefits:
- single TF-A build that works for RME and non-RME systems, when
build with ENABLE_FEAT_RME=2 (FEAT_STATE_CHECK)
- RMM loading is optional on RME systems
- SiP calls that leverages RME features to change the PAS of a memory
range from non-secure to secure is supported without need to enable
Realm PAS or RMM.
- FIRME Granule Management Interface (GMI) ABIs that handles
FEAT_RME_GPC2/FEAT_RME_GDI can be enabled without need to enable RMM
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I88d9d4e0491af2b4ae0307c018f2d4a71ee6693f
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RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.
Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.
For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192
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ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full RMM loading and handling.
While full CCA support requires all of these steps, some systems running
on FEAT_RME-capable cores do not need or want an RMM. However, such
systems still require TF-A page table entries to set the .NSE bit so
that TF-A accesses are correctly attributed to the ROOT world,
otherwise, enabling the MMU may cause the system to hang.
To address this, a new build option, ENABLE_FEAT_RME, is introduced. It
handles only the .NSE PTE setup and ignores the rest of the RME/RMM
initialization. ENABLE_FEAT_RME follows the ENABLE_FEAT_* convention and
supports values 0–2, with 2 enabling runtime detection.
Full RME functionality remains gated by ENABLE_RME, which now implicitly
enables ENABLE_FEAT_RME, allowing TF-A to run safely on FEAT_RME systems
without requiring an RMM.
Change-Id: I8391652842ff2e62a73b61829c6250c3805d4a4e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Set FIRME_SUPPORT to 1 under ENABLE_RME block to enable FIRME
interface as mandated by FIRME specification[1].
[1] https://developer.arm.com/documentation/den0149/latest/
Change-Id: I743251c202f5d8f48baab59e8ad57882c0b8374b
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.
The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.
This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.
Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Add an opt-in negative test mode that simulates a short read
for a selected image_id during image loading. This exercises
the partial-read error handling path and is intended for CI
validation only.
Disabled by default via build options.
Change-Id: I219b75898e1778c0b263f99a9370425098d52f8f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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* changes:
docs(rmm): update EL3-RMM contract
feat(rmmd): expand RMM SMC return registers
fix(cm): don't context switch GICv3 registers on NS<->RL transitions
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The GICv3 is architectured to solely manage interrupts targeted to
Normal and Secure world. It doesn't manage interrupts targeting the
more recently introduced Realm world. Hence the new RMMv2.0
specification mandates that EL3 should not save and restore
the GIC registers on a world switch. This change is not backward
compatible with RMMv1.x ABI.
Note the change in implementation of cm_el2_sysregs_context_save()
and cm_el2_sysregs_context_restore() API as GIC state is not
managed by these APIs anymore.
Add new build flag RMM_V1_COMPAT to support backward compatibility
with RMMv1.x. This flag is currently enabled by default.
This patch is a reworked version of the original patch at:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/45658
NOTE: If RMM_V1_COMPAT is not enabled, then RMM_EL3_IFC_VERSION
is bumped to 1.0 which makes it incompatible with an RMM supporting
0.x.
Change-Id: If4c53b85ef31091c254b383ed7b32c39124f0dbb
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
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* changes:
feat(build): add Mbed TLS submodule
fix(brcm): fix bad Mbed TLS check
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This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building configurations which require it, as the build system will
now look inside the `contrib` directory if the parameter is missing.
If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:
git submodule update --init --recursive
BREAKING-CHANGE: Mbed TLS is now included in the TF-A repository, and it
is no longer a requirement to pass `MBEDTLS_DIR` to the build system.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.
Change-Id: Iad777e77936d1c373065f17fe5c4aadc45e56b64
Signed-off-by: Chris Kay <chris.kay@arm.com>
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This patch introduces new build flags necessary for SP live activation
support and ensures all constraints are met.
BREAKING CHANGE: Temporarily fails to build
Change-Id: I17fba2ee935845816ae40067ca349b1eb9bb310c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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ARM_ARCH_MAJOR/MINOR is set to 9.2 when ENABLE_RME=1. It is not clear
why this is required and it is set early in the Makefile before the
platform specific Makefile. Also arch_features are setup based on
ARM_ARCH_MAJOR, ARM_ARCH_MINOR provided by the platform. So there is a
chance this could be overwritten by platform. This change removes
setting ARM_ARCH_MAJOR/MINOR to 9.2. If ENABLE_RME depends on other
architecture features then it must use ENABLE_FEAT option.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I1c74bb53e684d43c62e5f9b7259ebd76add84ff5
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* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STEP2
feat(docs): update the feature guide to mention FEAT_IDTE3
fix(cpufeat): remove the feature list from arch_features.h
docs(cpufeat): add analysis of 2022 features
fix(cpus): use hint instruction instead of the psb mnemonic
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The build system reads the POETRY variable and
internally sets host-poetry to the correct path
of the poetry tool. Update the build files to always
use the internal variable to run the tool.
Change-Id: I5acec9530a80661b0dcda8fba64abaa9d09165e9
Signed-off-by: Andrei Homescu <ahomescu@xwf.google.com>
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The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.
Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.
Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.
Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto extension
feat(crypto): enable access to SIMD crypto in BL1 and BL2
feat(crypto): enable floating point register traps in EL3
feat(crypto): build flag for SIMD crypto extensions for v8+ platform
refactor(build): add a default filter list for lib cflags
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Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest
Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_FEAT_CRYPTO_SHA3
to enable SIMD crypto extension for sha384 and sha512 in bootflow authentication
process for Arm platform greater than v8.0.
Change-Id: I6e52feb318136910d34cafd89319bf94f90e16fc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.
In current bl2_main there are two different code paths for RESET_BL2,
one handles BL2 running in EL1 and other for BL2 running in EL3.
When RME is enabled, BL2 always runs at EL3 but the current flow calls
bl2_early_platform_setup2, bl2_plat_arch_setup instead of
bl2_el3_early_platform_setup, bl2_el3_plat_arch_setup. Adding RME,
TRANSFER_LIST, ROMLIB support in bl2_el3_* helpers makes
arm_bl2_el3_setup.c almost identical to arm_bl2_setup.c.
This patch removes bl2_el3_plat helpers and related files. Now different
combinations of RESET_TO_BL2, ENABLE_RME are handled in common bl2_setup
routines in arm_bl2_setup.c. This helps to have common place to support
new features and build flags for BL2 irrespective of which EL the BL2
runs.
BREAKING-CHANGE: This patch also changes all existing platform files and
functions that use format bl2_el3_* to bl2_plat helpers. If any platform
or out-of-tree platforms that need to support running BL2 in EL1 or EL3
must now handle it in bl2_early_platform_setup2 and bl2_plat_arch_setup.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I8d332dbe2de1db3b69319496c8d04626cdcf4140
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FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply
saying it impacts execution at EL3. That's true, but FEAT_STATE_CHECKED
can still be allowed by being a bit clever about it.
First, the remainder of common code can be converted to use the
is_feat_ras_supported() helper instead of the `#if FEATURE` pattern.
There are no corner cases to consider there. The feature is either
present (and appropriate action must be taken) or the feature is not (so
we can skip RAS code).
A conscious choice is taken to check the RAS code in synchronize_errors
despite it being in a hot path. Any fixed platform that seeks to be
performant should be setting features to 0 or 1. Then, the
SCTLR_EL3.IESB bit is always set if ENABLE_FEAT_RAS != 0 since we expect
FEAT_IESB to be present if FEAT_RAS is (despite the architecture not
guaranteeing it). If FEAT_RAS isn't present then we don't particularly
care about the status of FEAT_IESB.
Second, platforms that don't set ENABLE_FEAT_RAS must continue to work.
This is true out of the box with the is_feat_xyz_supported() helpers, as
they make sure to fully disable code within them.
Third, platforms that do set ENABLE_FEAT_RAS=1 must continue to work.
This is also true out of the box and no logical change is undertaken in
common code.
Finally, ENABLE_FEAT_RAS is set to 2 on FVP. Having RAS implies that the
whole handling machinery will be built-in and registered as appropriate.
However, when RAS is built-in but not present in hardware, these
registrations can still happen, they will only never be invoked at
runtime.
Change-Id: I949e648601dc0951ef9c2b217f34136b6ea4b3dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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This patch adds a build macro ENABLE_FEAT_MORELLO which when set will
compile BL31 firmware with changes required to boot capability
aware software.
It also adds helper function in c and assmbly to check if morello
hardware is present and if morello capability is enabled or not.
CE field, bits [23:20] in ID_AA64PFR1_EL1 defines whether morello
architecture is present or not, 0b0000 indicates that it is absent
and 0b0001 indicates that it is present. While whether capabilities
are enabled or not is decided at runtime with ENABLE_FEAT_MORELLO build
option.
Reference: https://developer.arm.com/documentation/ddi0606/latest/
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: Ib16877acbfcb72c4bd8c08e97e44edc0a3e46089
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The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.
Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.
An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.
The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.
This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.
Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement
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Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).
This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b
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Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimisations to be made across compilation unit boundaries (i.e. C
files). This is especially useful in areas with lots of closely related
compilation units that operate on the same data structures (eg PSCI and
context management).
The only drawback is that LTO makes conditions ripe for the build to
heavily mangle all functions, making debugging a nightmare. So only
enable for release builds.
Note this will make object files unintepretable by objdump. Use lto-dump
instead.
BREAKING-CHANGE: LTO has been enabled by default, which may cause
unpredictable issues for platforms where the linker scripts have not
been designed with LTO in mind. Please report any issues to the
[mailing list](mailto:tf-a@lists.trustedfirmware.org).
Change-Id: Ia472aff1a23366d918abded7a1c5da695f2c4787
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3745f4506de123e3a4ff1e3ca6d5992f3b5c174a
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This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.
The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.
The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.
FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.
This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.
This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5
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* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2
feat(per-cpu): migrate amu_ctx to per-cpu framework
feat(per-cpu): migrate spm_core_context to per-cpu framework
feat(per-cpu): migrate psci_ns_context to per-cpu framework
feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework
feat(per-cpu): migrate rmm_context to per-cpu framework
feat(per-cpu): integrate per-cpu framework into BL31/BL32
feat(per-cpu): introduce framework accessors/definers
feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework
docs(changelog): add scope for per-cpu framework
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This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is designed to minimise
cache thrashing, and the linker layout ensures each CPU’s per-cpu data
is placed on a separate cache line. This isolation is expected to
improve performance when the per-cpu framework is enabled.
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie4d8b4e444971adbd9dba0446d1ab8cafaca1556
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