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authorSerge Semin <fancer.lancer@gmail.com>2022-08-06 20:41:22 +0300
committerSerge Semin <fancer.lancer@gmail.com>2026-08-06 13:00:40 +0300
commit0cbe89083d496b16902fa9911273334bfba6ab21 (patch)
treec2f9989604c2fcf7c0c88728007aca078c54568b
parentd3e74343c89b36539a70c8c2efdd4d2d38007a16 (diff)
downloadlinux-0cbe89083d496b16902fa9911273334bfba6ab21.tar.gz
linux-0cbe89083d496b16902fa9911273334bfba6ab21.zip
EDAC/synopsys: Add BT1 DDRC support
Baikal-T1 SoC is equipped with the DW uMCTl2 DDRC v2.61a with 32-bit DQ-bus accepting DDR2/DDR3 SDRAMs of up to 2 ranks, 1:2 HIF/SDRAM clocks rate ratio, HIF interface burst length of 8 Full DQ-bus words, 40-bit System/Application address width and 128-bits data width, 3 System address regions with block size 256MB. There is SEC/DED ECC capability with Scrub (RMW) and Scrubber features. Since the Baikal-T1 DDR controller supports Sideband ECC add the controller support to the DW uMCTL2 DDRC EDAC driver. The most of the parameters listed above will be autodetected except HIF burst length and SAR block size, which will be set by means of the Baikal-T1-specific initialization method. The controller compatible string "baikal,bt1-ddrc" will be used to attach the driver to the kernel device. It's chosen in accordance with the just updated DT-bindings. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> --- Changelog v4: - Explicitly set snps_ddrc_info.dq_width for Baikal-T1 DDRC for better maintainability. - Explicitly set sys_app_map.minsize to SZ_256M instead of using a helper macro DDR_MIN_SARSIZE.
-rw-r--r--drivers/edac/synopsys_edac.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 8254465078915..6e98bd89eb3b6 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -1364,6 +1364,21 @@ static int zynqmp_init_plat(struct snps_edac_priv *priv)
return 0;
}
+/*
+ * bt1_init_plat - Baikal-T1-specific platform initialization.
+ * @priv: DDR memory controller private data.
+ *
+ * Return: always zero.
+ */
+static int bt1_init_plat(struct snps_edac_priv *priv)
+{
+ priv->info.dq_width = SNPS_DQ_32;
+ priv->info.hif_burst_len = SNPS_DDR_BL8;
+ priv->sys_app_map.minsize = SZ_256M;
+
+ return 0;
+}
+
/**
* snps_get_dtype - Return the DDR memory chips type.
* @mstr: Master CSR value.
@@ -2496,6 +2511,7 @@ static void snps_mc_remove(struct platform_device *pdev)
static const struct of_device_id snps_edac_match[] = {
{ .compatible = "xlnx,zynqmp-ddrc-2.40a", .data = zynqmp_init_plat },
+ { .compatible = "baikal,bt1-ddrc", .data = bt1_init_plat },
{ .compatible = "snps,ddrc-3.80a" },
{ }
};