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| author | Serge Semin <fancer.lancer@gmail.com> | 2023-07-07 16:32:46 +0300 |
|---|---|---|
| committer | Serge Semin <fancer.lancer@gmail.com> | 2026-08-13 20:38:18 +0300 |
| commit | 8a521d160437a8b93a13c067b844aa406afa4cbe (patch) | |
| tree | 793e4ac3eef2c7b9b2456a81e782a7f9e9462f36 | |
| parent | 4d774b697acde32b8b45e6bb849b95ffc72b4f41 (diff) | |
| download | linux-8a521d160437a8b93a13c067b844aa406afa4cbe.tar.gz linux-8a521d160437a8b93a13c067b844aa406afa4cbe.zip | |
net: phy: marvell-88x2222: Convert to using bitfield helpers
bits.h and bitfield.h provides useful helpers with the bit fields
operations. Let's use them in driver instead of hard-coded bitwise shift
operation. The update concerns the PCS Host/Line mode select procedure
only.
Note while at it let's convert the mv2222_config_line() method to
collecting the fields in the local variable and then calling the
phy_write_mmd() method from a single place of the function. Thus it will
look a bit more coherent and the generated code smaller.
Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
| -rw-r--r-- | drivers/net/phy/marvell-88x2222.c | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/net/phy/marvell-88x2222.c b/drivers/net/phy/marvell-88x2222.c index 48ed20728314c..c29fb6a52a5dd 100644 --- a/drivers/net/phy/marvell-88x2222.c +++ b/drivers/net/phy/marvell-88x2222.c @@ -7,6 +7,8 @@ * 1000Base-X or 10GBase-R on the line side. * SGMII over 1000Base-X. */ +#include <linux/bitfield.h> +#include <linux/bits.h> #include <linux/module.h> #include <linux/phy.h> #include <linux/delay.h> @@ -18,10 +20,12 @@ /* Port PCS Configuration */ #define MV_PCS_CONFIG 0xF002 +#define MV_PCS_HOST_PCS_SELECT GENMASK(6, 0) #define MV_PCS_HOST_XAUI 0x73 -#define MV_PCS_LINE_10GBR (0x71 << 8) -#define MV_PCS_LINE_1GBX_AN (0x7B << 8) -#define MV_PCS_LINE_SGMII_AN (0x7F << 8) +#define MV_PCS_LINE_PCS_SELECT GENMASK(14, 8) +#define MV_PCS_LINE_10GBR 0x71 +#define MV_PCS_LINE_1GBX_AN 0x7B +#define MV_PCS_LINE_SGMII_AN 0x7F /* Port Reset and Power Down */ #define MV_PORT_RST 0xF003 @@ -193,20 +197,25 @@ static bool mv2222_is_sgmii_capable(struct phy_device *phydev) static int mv2222_config_line(struct phy_device *phydev) { struct mv2222_data *priv = phydev->priv; + u16 val; + + val = FIELD_PREP(MV_PCS_HOST_PCS_SELECT, MV_PCS_HOST_XAUI); switch (priv->line_interface) { case PHY_INTERFACE_MODE_10GBASER: - return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, - MV_PCS_HOST_XAUI | MV_PCS_LINE_10GBR); + val |= FIELD_PREP(MV_PCS_LINE_PCS_SELECT, MV_PCS_LINE_10GBR); + break; case PHY_INTERFACE_MODE_1000BASEX: - return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, - MV_PCS_HOST_XAUI | MV_PCS_LINE_1GBX_AN); + val |= FIELD_PREP(MV_PCS_LINE_PCS_SELECT, MV_PCS_LINE_1GBX_AN); + break; case PHY_INTERFACE_MODE_SGMII: - return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, - MV_PCS_HOST_XAUI | MV_PCS_LINE_SGMII_AN); + val |= FIELD_PREP(MV_PCS_LINE_PCS_SELECT, MV_PCS_LINE_SGMII_AN); + break; default: return -EINVAL; } + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, val); } /* Switch between 1G (1000Base-X/SGMII) and 10G (10GBase-R) modes */ |