net: stmmac: Add AXI ACE attributes setup

If the DW QoS Ether/XGMAC/XLGMAC/etc are synthesized into the system with
the AXI4 master bus it's possible to specify the cacheability attributes
of the memory accesses. In the meantime if the controller is defined in
the system as DMA-cache-coherent then any cacheable attributes can be
utilized. This shall significantly speed up the controller IO performance.
In our case the iperf3 got x4 faster on a single thread test reaching the
practical maximum of the DW XGMAC controller!

Let's provide a new fine-tuning platform AXI cache coherency parameter
then. So if it's initialized with true then the driver considers that the
device is DMA-coherent and enables the "Write-back No-allocate" memory
access proto with Outer Shareable domain. Thus an Rx-es will be written to
the cache and Tx-es will be read from the cache if there are respective
entries are. Otherwise the data will be read directly from the memory.

Signed-off-by: Serge Semin <fancer.lancer@gmail.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 32352a216567e..b96bcb3905a7e 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -117,6 +117,7 @@ struct stmmac_axi {
 	bool axi_fb;
 	bool axi_mb;
 	bool axi_rb;
+	bool axi_cc;
 };
 
 struct stmmac_rxq_cfg {