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| author | Shaikh Kamaluddin <shaikhkamal2012@gmail.com> | 2026-08-24 19:19:57 +0530 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-08-31 09:40:35 -0700 |
| commit | 04a7b330c8b60dfff200d9a32dd6615f97b59d07 (patch) | |
| tree | c495a594a5eeb13daa45cfa74988e64adaa1640a /scripts/Makefile.thinlto | |
| parent | 2c73cda8908f1275b0ecf81ae540a3bc2a90fc30 (diff) | |
| download | linux-next-04a7b330c8b60dfff200d9a32dd6615f97b59d07.tar.gz linux-next-04a7b330c8b60dfff200d9a32dd6615f97b59d07.zip | |
cxl/mce: Avoid alias page retirement for corrected errors
cxl_handle_mce() offlines the aliased page of an Extended Linear Cache
(ELC) region for any MCE with a usable address in the region. This
includes corrected errors, needlessly reducing usable memory.
Skip ELC alias retirement when mce_is_correctable() identifies the
reported error as corrected. Uncorrected errors with a usable address
in the ELC region continue to retire the aliased page as before.
mce_usable_address() already implements the per-vendor checks that
determine whether the reported address is usable, so no separate
memory-error classification is needed.
On AMD, a corrected legacy bank 4 DRAM ECC error (XEC 8) reports a
usable address and retired the aliased page before this change.
Tested under QEMU with Intel Skylake-Server and AMD EPYC-Milan models.
Fixes: 516e5bd0b6bf ("cxl: Add mce notifier to emit aliased address for extended linear cache")
Signed-off-by: Shaikh Kamaluddin <shaikhkamal2012@gmail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20260824134957.11085-1-shaikhkamal2012@gmail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts/Makefile.thinlto')
0 files changed, 0 insertions, 0 deletions
