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| author | Matthew Auld <matthew.auld@intel.com> | 2026-09-02 13:41:21 +0100 |
|---|---|---|
| committer | Matthew Auld <matthew.auld@intel.com> | 2026-09-03 11:33:23 +0100 |
| commit | bab69ad31cd35b282921efe825a496cf89dd7374 (patch) | |
| tree | 3fdd14188862df3bc6cbda5b958a2f0d6a94832c /scripts | |
| parent | d00b7f4f03bbeb2efad872f1686130e18c2b4141 (diff) | |
| download | linux-next-bab69ad31cd35b282921efe825a496cf89dd7374.tar.gz linux-next-bab69ad31cd35b282921efe825a496cf89dd7374.zip | |
drm/xe/vram: revamp CPU VRAM mapping
Previously, we called devm_ioremap_wc() for the entire PCI LMEM BAR (which
can be significantly larger than usable memory, e.g., mapping 16G for a
10G card), and then simply assigned subsets of this global mapping to each
tile.
By moving the devm_ioremap_wc() call into vram_region_init() and mapping
on a per-tile basis, we restrict the virtual address space to exactly
the usable_size of each tile. The other big win is that the core kernel
will place a guard page at the end of each per-tile mapping to help
catch OOB CPU writes (e.g. into the flat CCS storage) by triggering an
immediate page fault instead of silent memory corruption.
As a consequence the global vram->mapping is now NULL. But that was
unused anyway, with CPU access already correctly routed through the per
tile mapping.
v2 (Sashiko)
- Make sure to update the panic flow to now use the root tile.
Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260902124117.918018-10-matthew.auld@intel.com
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions
