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21 hoursMerge branch 'headers' of git://git.infradead.org/users/willy/pagecache.gitMark Brown
# Conflicts: # net/ceph/osd_client.c
22 hoursMerge branch 'usb-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
22 hoursMerge branch 'master' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
22 hoursMerge branch 'master' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git # Conflicts: # tools/testing/selftests/bpf/prog_tests/verifier.c
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
22 hoursMerge branch 'ti-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
22 hoursMerge branch 'stm32-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
22 hoursMerge branch 'next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git
22 hoursMerge branch 'next' of https://github.com/Broadcom/stblinux.gitMark Brown
22 hoursMerge branch 'asahi-soc/for-next' of https://github.com/AsahiLinux/linux.gitMark Brown
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
22 hoursMerge branch 'mm-nonmm-unstable' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm # Conflicts: # init/main.c
22 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/mm/linux.git
22 hoursMerge branch 'kexec-fixes' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git
22 hoursMerge branch 'fixes' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git
22 hoursMerge branch 'fixes' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
26 hoursMerge branch 'master' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git/
26 hoursMerge branch 'for-next/fixes' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
28 hoursarm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HATMarek Vasut
Add a DT overlay to bind the WaveShare 2-Channel Isolated CAN FD Expansion HAT on the Retronix R-Car V4H Sparrow Hawk board. Current device link is at https://www.waveshare.com/2-ch-can-fd-hat.htm Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260909151423.28358-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: sparrow-hawk: Align MSIOF1 PFC node name with labelMarek Vasut
Align MSIOF1 PFC node name with label to improve consistency. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260909151341.28322-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: white-hawk: Add second mini-DP output supportGeert Uytterhoeven
Add support for the mini-DisplayPort connector on the White Hawk BreakOut board. This connector is driven by a TI SN65DSI86 DSI-to-eDP bridge, which in turn gets the pixel data from the second DSI channel on the R-Car V4H SoC. Note that this port is not present on the White Hawk Single development board. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [tomi.valkeinen: added status=okay for dsc] Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Link: https://patch.msgid.link/20260907-rcar-du-dsc-v6-6-f8ef711a7494@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: sparrow-hawk: Enable DisplayPort by adding DSCMarek Vasut
DisplayPort on the Sparrow Hawk board uses an SN65DSI86 bridge, which in turn gets the video stream from the SoC's DSI1 port. The DSI1 pipeline has a DSC block in between the DU and the DSI1. However, there was no DSC driver in Linux and also the DSC was not defined in the dts files, and thus the DisplayPort output did not work. Now that we have DSC defined in the SoC dts file (r8a779g0.dtsi), enable DSC for sparrowhawk. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [tomi.valkeinen: separated the sparrow hawk changes from the soc changes] Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260907-rcar-du-dsc-v6-5-f8ef711a7494@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r8a779g0: Add DSCMarek Vasut
The Renesas DSC Display Stream Compression is a bridge embedded in the Renesas R-Car V4H SoC. The bridge is placed between the DU and DSI1 units. The current dtsi file does not represent the DSC at all, and thus the pipeline for DSI1 has not been functional. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [tomi.valkeinen: separated the sparrowhawk changes] Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260907-rcar-du-dsc-v6-4-f8ef711a7494@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r8a779h0: Add GICv3 ITS and update PCIe nodeMarek Vasut
This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this SoC can use it. Add GIC ITS node into GIC node, update interrupt-map and add msi-map into PCIe controller node. The GIC ITS does have master interface to issue transactions to RAM. The interface does support cacheable transactions, however, it does not support shareable attribute, because the AXI port signals are tied to inactive in this implementation. Therefore, add "dma-noncoherent" DT property into the GIC ITS subnode. The GIC redistributor does not have cacheable/shareable, therefore add "dma-noncoherent" DT property into the GIC node. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260906140134.492084-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a08g046: Add LVDS nodeBiju Das
Add LVDS node to RZ/G3L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260826174854.199139-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a08g046: Add DU and DSI nodesBiju Das
Add DU and DSI nodes to RZ/G3L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260826174854.199139-11-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a08g046: Add VSPD nodeBiju Das
Add VSPD node to RZ/G3L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260826174854.199139-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a08g046: Add FCPVD nodeBiju Das
Add FCPVD node to RZ/G3L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260826174854.199139-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: rzt2h-n2h-evk: Mark XSPI1 boot partitions read-onlyLad Prabhakar
Mark the BL2 and FIP partitions on XSPI1 as read-only to prevent them from being modified through the MTD partition interface. The corresponding boot partitions on XSPI0 are already marked read-only. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260826112821.194877-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a09g047e57-smarc: Update CAN transceiversGeert Uytterhoeven
The dual-channel TCAN1046V-Q1 CAN Transceiver on the RZ/G3E SMARC EVK is currently modelled as two TCAN1042 instances. Improve hardware description by describing the actual transceiver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/2a759a486337e4cc8156bc94079471a6552faefc.1787669487.git.geert+renesas@glider.be
28 hoursarm64: dts: renesas: rzt2h-n2h-evk: Enable RTC supportLad Prabhakar
Enable RTC support on RZ/T2H and RZ/N2H EVKs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260824075936.2904336-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a09g087: Add RTC nodeLad Prabhakar
Add Real Time Clock (RTC) node to SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260824075936.2904336-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a09g077: Add RTC nodeLad Prabhakar
Add Real Time Clock (RTC) node to SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260824075936.2904336-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: Use hyphens in node namesKrzysztof Kozlowski
DTS coding style encourages to use hyphens instead of underscores in node names. DTC W=2 warns about underscores. Improve existing code because apparently people copy it instead of following DTS coding style for new submissions. Semi-manual validation by checking if no new nodes appeared: $ for i in dts-old/*/*dtb dts-old/*/*/*dtb; do echo $i; fdtdump ${i} > ${i}.fdt ; fdtdump dts-new/${i#dts-old/} > dts-new/${i#dts-old/}.fdt ; diff -ubB ${i}.fdt dts-new/${i#dts-old/}.fdt ; done | grep -v ' {' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260822075813.199336-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: Add LCDC overlays for RZ/T2H and RZ/N2H EVKsLad Prabhakar
Add DT overlay support for enabling the DU/LCDC pipeline on the RZ/T2H and RZ/N2H evaluation kits when fitted with an ADV7513 HDMI transmitter on CN15/CN20. Share the common ADV7513 and LCDC pin configuration between the two overlays. Disable board functions whose pins are reassigned to LCDC, including the affected LEDs, SDHI0 on the RZ/T2H EVK, and I2C0 on the RZ/N2H EVK. Move the LED8 and LED9 preprocessor conditionals inside the node definitions so that the nodes remain present in the base DTS. This allows the LCDC overlays to reference and disable the LEDs when their pins are reassigned to display functions. Configure the LCDC data and clock pins with slew-rate setting 1 as recommended by the hardware manual. Use slew-rate setting 0 for the HSYNC, VSYNC and DE pins, as testing with the ADV7513 showed unstable display output and visible flicker when these synchronization signals were configured for fast slew rate. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260819183829.3953529-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: rzt2h-n2h-evk: Use consistent switch notationLad Prabhakar
The switch comments in the board DT files use inconsistent notation, with some references written as "SWx-y" and others as "SWx[y]" (and "DSWx-y"/ DSWx[y] for the DIP switches on the RZ/N2H EVK). Standardise on the "SWx[y]" / "DSWx[y]" form throughout both files so switch references use a consistent notation. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260819183829.3953529-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a09g087: Adjust CPG register region sizesLad Prabhakar
Increase the sizes of both CPG register regions from 64 KiB to 128 KiB. On the RZ/N2H SoC, the CPG/MSSR block is a multi-function block where, apart from clock and reset handling, it supports other features including clock monitoring, write protection, and peripheral configuration registers. Expand the mapped register regions to cover the entire register space of this block so these additional features can be utilized. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260817192540.423994-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r9a09g077: Adjust CPG register region sizesLad Prabhakar
Increase the sizes of both CPG register regions from 64 KiB to 128 KiB. On the RZ/T2H SoC, the CPG/MSSR block is a multi-function block where, apart from clock and reset handling, it supports other features including clock monitoring, write protection, and peripheral configuration registers. Expand the mapped register regions to cover the entire register space of this block so these additional features can be utilized. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260817192540.423994-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodesMarek Vasut
This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this SoC can use it. Add GIC ITS node into GIC node, update interrupt-map and add msi-map into PCIe controller node. The GIC ITS does have master interface to issue transactions to RAM. The interface does support cacheable transactions, however, it does not support shareable attribute, because the AXI port signals are tied to inactive in this implementation. Therefore, add "dma-noncoherent" DT property into the GIC ITS subnode. The GIC redistributor does not have cacheable/shareable, therefore add "dma-noncoherent" DT property into the GIC node. Co-developed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260809200429.843212-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: r8a78000: Add MDLC nodesGeert Uytterhoeven
Add device nodes for the Module Control (MDLC) blocks on the R-Car X5H (R8A78000) SoC. Complete hardware desciption of all (H)SCIF serial ports, by linking them to an MDLC for power domains and resets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/9b7f96352ef5fe08e7003169710a9af874fccb68.1785941595.git.geert+renesas@glider.be
28 hoursarm64: dts: renesas: r8a78000: Add CPG nodeGeert Uytterhoeven
Add a device node for the Clock Pulse Generator (CPG) on the R-Car X5H (R8A78000) SoC. Convert all (H)SCIF serial ports from dummy to CPG clocks, removing the need for any dummy clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/03a40ce94e01a5a390493b8c711c299d328a2db3.1785941595.git.geert+renesas@glider.be
28 hoursarm64: dts: renesas: r9a09g047e57-smarc: Set I2C1 clock frequency to 1 MHzTommaso Merciai
On the SMARC carrier board I2C1 only carries the DA7212 audio codec. Override the 100 kHz SoC default to 1 MHz. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260803132828.3249424-4-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: Correct white-space styleKrzysztof Kozlowski
Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260801210321.383773-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 hoursarm64: dts: renesas: beacon: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9131RNX reference manual [1] DS00002841D page 131 FIGURE 6-2: POWER SEQUENCE TIMING INTERNAL REGULATORS does not indicate how long should the system wait after deassertion of the PHY reset and before starting communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ9131RNX reference manual [1] DS00002841D page 131 FIGURE 6-2: POWER SEQUENCE TIMING INTERNAL REGULATORS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9131RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/00002841D.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130539.11287-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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