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path: root/drivers/pinctrl
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19 hoursMerge branch 'headers' of git://git.infradead.org/users/willy/pagecache.gitMark Brown
# Conflicts: # net/ceph/osd_client.c
19 hoursMerge branch 'pinctrl-qcom/for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
19 hoursMerge branch 'renesas-pinctrl' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
19 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
3 dayspinctrl: renesas: rzg2l: Add RZ/G3S support for selecting I3C power sourceClaudiu Beznea
The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register to select between these two options. Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260904125425.412632-6-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 dayspinctrl: renesas: rzg2l: Unify power source handlingClaudiu Beznea
The previous code handled power sources using a mixture of power source specific definitions and lookups in the available_ps[] array. Unify the power source handling by introducing struct rzg2l_pinctrl_ps_desc, whose purpose is to describe a power source through its power source value, associated register value, associated capabilities (e.g. Ethernet), and associated IOLH index. Introduce two new functions, rzg2l_ps_to_desc() and rzg2l_pwr_reg_val_to_desc(), using the RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC() macro, as their implementations are similar. These functions retrieve a power source descriptor based on either a power source value or a power source register value. Other functions that need to perform power source specific operations can call them to retrieve the corresponding power source descriptor. The register values for the soft power sources were kept to zero since they are not used across the driver's code. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260904125425.412632-4-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 dayspinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfgClaudiu Beznea
Drop the QSPI and OTHER_POC register defines, which are SoC specific and accessible through struct rzg2l_hwcfg::{qspi, other_poc}. While at it move the assignement of rzg2l_hwcfg->regs->qspi upper to have the initializations as sorted (by offsets) as possible. Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260904125425.412632-3-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 dayspinctrl: renesas: rzg2l: Generalize power source codeClaudiu Beznea
The current functions used to get/set the pin power source check the OTHER_POC register, which is specific to the RZ/G3L SoC only. To allow the code to be extended for other power source functionalities (e.g. I3C on RZ/G3S), generalize the functions used to get/set the pin power source. For this, introduce the struct rzg2l_register_masks data structure whose purpose is to store SoC specific register bit masks. The members of this structure are then used in rzg2l_caps_to_pwr_reg() to retrieve the bitmask corresponding to a SoC specific power source capability. The conversion between HW specific power source values and SW specific power source values is now handled through rzg2l_pwr_reg_val_to_ps() and rzg2l_ps_to_pwr_reg_val(). Finally, to keep the code generic, the register update in rzg2l_set_power_source() was changed to a read-modify-write approach to cover all cases. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260904125425.412632-2-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 dayspinctrl: qcom: ipq5210: Publish the OF module aliashpp.iscas
The IPQ5210 TLMM platform driver can be a module and matches through ipq5210_tlmm_of_match. This table is not published for OF modalias matching. Publish the existing table, preserving arch_initcall ordering and the shared MSM pinctrl probe. Fixes: a549fe22376f ("pinctrl: qcom: Introduce IPQ5210 TLMM driver") Signed-off-by: hpp.iscas <hppiscas@163.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260905134340.67477-1-hppiscas@163.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
3 dayspinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functionsShawn Guo
QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 respectively. Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() stops at the first entry matching the requested function, which means mux value 1 was always selected and the I2C lanes could never be muxed out. In practice i2c9 and i2c10 got the UART lanes and did not work, while uart9 and uart10 happened to be muxed correctly. Give each lane pair its own function, following the _01/_23 naming already used for the same hardware arrangement by the shikra, eliza, hawi and maili TLMM drivers. Both functions still cover the full pin pair, so a single pinctrl state per protocol remains sufficient. Drop gpio129/gpio130 from the SE2 group list, since those pins belong to SE3 and were never reachable through the SE2 function. Also rename QUP1 SE2/SE3 functions in the binding doc accordingly. While at it, add missing "gpio", "qup3_se0_mira" and "qup3_se0_mirb" to the binding function enum to get the list complete. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260830030201.135637-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
7 dayspinctrl: intel: Try to retrieve driver data for pure platform driversAndy Shevchenko
The Denverton pinctrl device can be instantiated by the Intel LPC driver as an MFD platform device named "denverton-pinctrl". On affected systems the platform device does not carry the INTC3000 ACPI match data itself. As a result, intel_pinctrl_probe_by_hid() fails to obtain the SoC data using device_get_match_data() and returns -ENODATA. This might be also true for other platforms that can be enumerated by ACPI _HID. Fix the above by trying the pure platform driver data in case the firmware node is not set or doesn't carry the necessary information. Reported-by: Radek Válko <rvalko@lipicko.cz> Closes: https://lore.kernel.org/r/20260827184259.32386-1-rvalko@lipicko.cz Tested-by: Radek Válko <rvalko@lipicko.cz> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 dayspinctrl: intel: constify parameter in intel_pinctrl_get_soc_data()Andy Shevchenko
The parameter of intel_pinctrl_get_soc_data() is not going to be modified. Mark it with const qualifier. Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 dayspinctrl: intel: Move intel_pinctrl_get_soc_data() upper in the codeAndy Shevchenko
While it's exported function, move it upper in the code to be on top of the local user. This brings a consistency to the follow change that will introduce similar helper for the intel_pinctrl_probe_by_hid(). Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8 dayspinctrl: qcom: Add Kuno pinctrl driverHardeep Sharma
Add the TLMM pinctrl driver for the Qualcomm Kuno platform, supporting 110 GPIOs and their pin multiplexing, pin configuration and gpiolib interface through the common pinctrl-msm driver. Signed-off-by: Hardeep Sharma <hardeep.sharma@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260827-kuno-soc-support-v5-9-6d47636a8f09@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
8 dayspinctrl: qcom: spmi-gpio: Add PMAU0102 GPIO supportDhruvin Rajpura
Add support for the PMAU0102 PMIC GPIO block, which has 12 GPIOs, used on Nord platform. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260830042939.144376-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
9 dayspinctrl: qcom: hawi-lpass-lpi: add Hawi LPASS LPI TLMMPrasad Kumpatla
Add pin controller driver for the Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. The controller has 23 GPIOs with SoundWire, I2S, DMIC, VA I2S, ext_mclk1 and slimbus mux functions. Two pins (gpio13, gpio22) require 6 mux slots due to a test_bus entry occupying a middle hardware slot. Add LPI_PINGROUP6 macro to pinctrl-lpass-lpi.h to support pins with 5 alternate functions. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260821113548.2686650-3-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
10 dayspinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3LBiju Das
Add power-on control (POC) support for SD channels 1 and 2 on the RZ/G3L SoC (r9a08g046). Introduce PIN_CFG_IO_VMC_SD2 capability flag (bit 22) and SD_CH2_POC register offset (0x3024). Extend rzg2l_caps_to_pwr_reg() to return SD_CH2_POC when PIN_CFG_IO_VMC_SD2 is set. Replace RZG3L_MPXED_PIN_FUNCS() with RZG2L_MPXED_COMMON_PIN_FUNCS() for port PG and PH pins, dropping PIN_CFG_SOFT_PS which is inappropriate for SD pins, and annotate them with PIN_CFG_IO_VMC_SD1 and PIN_CFG_IO_VMC_SD2 respectively. Annotate all RZ/G3L SD0 dedicated pins (CLK, CMD, RST#, DS, DAT0–DAT7) with PIN_CFG_IO_VMC_SD0 so that power-source register lookups work correctly for those pins. Add sd_ch2 field to rzg2l_register_offsets and rzg2l_pinctrl_reg_cache to save and restore the SD_CH2_POC register across suspend/resume cycles. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260723154154.319674-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-25headers: Remove swap.h from suspend.hMatthew Wilcox (Oracle)
Nothing in suspend.h needs swap.h. However, many files indirectly depend on some of swap.h's dependencies, so this is a large cross-subsystem patch. Stats: 42 are missing includes of interrupt.h (the question of why swap.h brings in interrupt.h remains unanswered). 10 missing includes of seq_file.h 5 missing includes of swap.h (obviously all files could have just added swap.h, but I preferred to bring in a more minimal inclusion set) 3 missing includes of highmem.h 2 missing includes of device.h 2 missing includes of string_choices.h 1 missing include of cacheflush.h 1 missing include of dma-direction.h 1 missing include of kthread.h 1 missing include of pagemap.h 1 missing include of string_helpers.h 1 missing include of writeback.h I tried to follow whatever conventions appeared to be in use for the various subsystems I touched; for example I added string_choices.h to drm_print.h instead of individually to each driver which used the functions declared there. Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
2026-08-24Merge tag 'pinctrl-v7.3-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...
2026-08-18Merge tag 'v7.2' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next Linux 7.2
2026-08-16Merge tag 'pinctrl-qcom-updates-for-v7.3-rc1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel Qualcomm pinctrl updates for v7.3-rc1 New drivers: - add pinctrl drivers for Maili TLMM and Elize LPASS LPI TLMM controllers Driver updates: - acknowledge interrupts for the PDC interrupt controller in pinctrl-msm - implement irq_get/set_irqchip_state() for pinctrl-msm - add support for a new model to Qualcomm pinctrl-spmi-gpio - drop some dead code from qcom pinctrl modules Devicetree bindings: - document new TLMM controllers and the new model for the SPMI GPIO Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-16Merge tag 'pinctrl-qcom-fixes-for-v7.2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel Qualcomm pin control fixes for v7.2 - fix intr_target_width for summary interrupt routing in pinctrl-shikra Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: meson: sync some modify from A4Xianwei Zhao
Set the drive strength before enabling the output to avoid enabling the output with an unintended drive strength. Also return the actual output enable state from PIN_CONFIG_OUTPUT_ENABLE instead of always reporting it as enabled. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: meson: a4: Add input enable pin configurationXianwei Zhao
Add support for PIN_CONFIG_INPUT_ENABLE in the Amlogic A4 pinctrl driver. Use the existing output enable control to configure the input enable state, since the hardware uses the same control with inverse semantics. Also update PIN_CONFIG_OUTPUT_ENABLE handling to return the actual output enable state instead of treating any non-zero value as enabled. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: realtek: rtd1625: remove unused group name spdif_selYu-Chun Lin
Remove the undefined "spdif_sel" from rtd1625_iso_spdif_in_coaxial_groups to clean up the code. Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13Yu-Chun Lin
Fix a typo in the base_bit of RTD1625_VE4_GPIO_13. It was incorrectly set to 18, which overlaps with GPIO 16. Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-11Merge tag 'intel-pinctrl-v7.3-1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v7.3-1 * Enable CPLD pin control on UP Xtreme i12 board * Miscellaneous cleanup Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-11Revert "Merge branch 'ib-rsk7204' into devel"Linus Walleij
This reverts commit d922b54e942ee9c798b0d688b025362a24d864ea, reversing changes made to 3f0245e23a176e78f00a760291b8e4f88d01d77e. The SH maintainer has indicated that he want to carry these changes in the SH tree instead, and need more time to review and merge the changes, so reverting it out from my tree. Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-10pinctrl: rockchip: Add RV1106 pinctrl supportSimon Glass
Add pinctrl support for the Rockchip RV1106, based on the vendor kernel in the Luckfox Pico SDK [1] at commit 824b817f8 (a Linux 5.10.160 kernel tree). Each GPIO bank has its own IO control (IOC) register block, referenced by the rockchip,grf phandle of the bank node; the register offsets are relative to the bank's own block. The drive strength uses the RK3568-style exponential encoding and only pins 0-6 of GPIO0 have drive-strength registers. The RV1103 is a package variant of the RV1106 with fewer pins and uses the same pin controller. [1] https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-10pinctrl: rockchip: Decode drive strength in the get functionSimon Glass
The decoding of the 2-bit and 8-bit level drive-strength values sits in rockchip_set_drive_perpin(), where it is unreachable: the SoCs whose banks declare these drive types (RK3506 and RV1103B) take the early ctrl->type branch in the set path, and the read-and-decode logic in a set function has no purpose. Meanwhile rockchip_get_drive_perpin() lacks the decoding, so pin_config_get() and the debugfs output report -EINVAL for these SoCs. Move the two cases to rockchip_get_drive_perpin(), where they belong. Fixes: dbd2317d7b9f ("pinctrl: rockchip: Add rk3506 pinctrl support") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: fix PINCTRL_GENERIC_MUX not always being selectableAlvin Šipraga
CONFIG_MULTIPLEXER can only be enabled indirectly. If it's not already enabled, then CONFIG_PINCTRL_GENERIC_MUX cannot be selected at all in menuconfig. That's because it depends on MULTIPLEXER. Follow similar consumers of the multiplexer core and select MULTIPLEXER instead. This way the driver will be visible in menuconfig as long as PINCTRL is selected. Fixes: 34acc5a8adfb ("pinctrl: add generic board-level pinctrl driver using mux framework") Signed-off-by: Alvin Šipraga <alvin.sipraga@analog.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: add support of an7563 SoCMikhail Kshevetskiy
This patch adds support of Airoha an7563 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: try to find chip scu node by phandle firstMikhail Kshevetskiy
The "airoha,en7581-chip-scu" is not a good compatible string in the en7523 case. Let's search chip scu regmap with "airoha,chip-scu" phangle first and fallback to SoC specific chip scu compatible string on failure. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: add support of en7523 SoCMikhail Kshevetskiy
This patch adds support of Airoha en7523 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: add support for olt pinmuxMikhail Kshevetskiy
Add support for olt pin function for olt pin group. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: add support for pon_alt pinmuxMikhail Kshevetskiy
Add support for pon pin function for pon_alt pin group. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: add support for npu_uart pinmuxMikhail Kshevetskiy
Add support for uart pin function for npu_uart pin group. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: rename registers to match its an7583 namesMikhail Kshevetskiy
In the an7581 case the register at 0x1FA20214 is called RG_GPIO_2ND_I2C_MODE. The same register in the an7583 case is called RG_SW_TOD_1PPS_MODE. Let's rename this register to avoid potential confuse. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: remove an7583 prefix from variable names and ↵Mikhail Kshevetskiy
definitions We have only an7583 specific code in the pinctrl-an7583 kernel module, so an7583 prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7581: remove en7581 prefix from variable namesMikhail Kshevetskiy
We have only an7581 specific code in the pinctrl-an7581 kernel module, so 'en7581_' prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: split driver on shared code and SoC specific driversMikhail Kshevetskiy
Split combined an7581/an7583 source file on a * shared pinctrl code (pinctrl-airoha.c) * an7581 specific pinctrl driver (pinctrl-an7581.c) * an7583 specific pinctrl driver (pinctrl-an7583.c) Ininialization code was adapted a bit to work properly for shared and SoC specific cases. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: move common definitions to the separate headerMikhail Kshevetskiy
Let's move the SoC independent definitions and declarations of structures required for Airoha SoC-specific pinctrl drivers to a common header. Later we'll have several SoC-specific drivers, so this step is necessary. We will not move to the common header file other register addresses, register bitfields definitions and macroses that use SoC specific information. We will keep SoC specific definitions inside SoC specific files. No functional changes. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: statically allocate gpio regs structureMikhail Kshevetskiy
just a small refactoring to collect all gpio register information in the one statically allocated structure. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: remove not needed irq_type[] arrayMikhail Kshevetskiy
irq_type[] array inside airoha_pinctrl_gpiochip structure is not actually necessary. Use trigger type from 'struct irq_data' instead. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: fix edge-triggered interrupts handlingMikhail Kshevetskiy
Edge-triggered interrupts are handled incorrectly because of * no irq_ack() handler was defined, * no handle_level_irq() handler was used, This patch probably fixes an issue Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: fix IRQ mask/unmask codeMikhail Kshevetskiy
When using IRQCHIP_IMMUTABLE, airoha_irq_unmask() must manually call gpiochip_enable_irq() and airoha_irq_mask() must call gpiochip_disable_irq(). Without these calls, gpiolib never sets the GPIOD_FLAG_IRQ_IS_ENABLED bit. Because this bit is missing, gpiod_direction_output() will not realize the pin is actively used as an interrupt. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: add missed IRQ resource helpersMikhail Kshevetskiy
Without hooking .irq_request_resources, gpiolib cannot set GPIOD_FLAG_USED_AS_IRQ. This breaks pin direction locking and can allow userspace or another driver to reconfigure an active IRQ pin as an output Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: fix getting gpiochip/pinctrl pointers in the IRQ handling codeMikhail Kshevetskiy
airoha_irq_unmask(), airoha_irq_mask(), airoha_irq_type() functions impements brain damaged logic to retrieve gpiochip and pinctrl pointers. Details: gpiochip = irq_data_get_irq_chip_data(data); will initialize gpiochip variable with data->chip_data value. This value initialized inside gpiochip_irq_map() function static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { struct gpio_chip *gc = d->host_data; ... irq_set_chip_data(irq, gc); ... } Thus gpiochip variable of 'struct airoha_pinctrl_gpiochip *' type will be initialized with a pointer to a variable of 'struct gpio_chip' type. Luckily, gpio_chip is the first element of airoha_pinctrl_gpiochip, so gpiochip pointer will get a correct value. This patch implements correct logic of getting gpiochip and pinctrl pointers. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: minor improvementsMikhail Kshevetskiy
Changes: * use field_get() macro instead of direct bit operations * improve error handling Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: add set_direction() helper for gpio_chipMikhail Kshevetskiy
The patch creates set_direction() helper for gpio_chip abstraction. It also implements/reimplements some function using newly defined helper. This is cosmetic patch used to place gpio_chip specific code together. No functional changes. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-10 08:11:16 +0000