path: root/drivers/gpu/drm/xe/xe_vram.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2021-2024 Intel Corporation
 */

#include <kunit/visibility.h>
#include <linux/pci.h>

#include <drm/drm_managed.h>
#include <drm/drm_print.h>

#include "regs/xe_bars.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_regs.h"
#include "xe_assert.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt_mcr.h"
#include "xe_map.h"
#include "xe_migrate.h"
#include "xe_mmio.h"
#include "xe_sriov.h"
#include "xe_tile.h"
#include "xe_tile_sriov_vf.h"
#include "xe_ttm_vram_mgr.h"
#include "xe_vram.h"
#include "xe_vram_types.h"

static bool resource_is_valid(struct pci_dev *pdev, int bar)
{
	if (!pci_resource_flags(pdev, bar))
		return false;

	if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
		return false;

	if (!pci_resource_len(pdev, bar))
		return false;

	return true;
}

static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *lmem_bar)
{
	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);

	if (!resource_is_valid(pdev, LMEM_BAR)) {
		drm_err(&xe->drm, "pci resource is not valid\n");
		return -ENXIO;
	}

	lmem_bar->io_start = pci_resource_start(pdev, LMEM_BAR);
	lmem_bar->io_size = pci_resource_len(pdev, LMEM_BAR);
	if (!lmem_bar->io_size)
		return -EIO;

	/* XXX: Need to change when xe link code is ready */
	lmem_bar->dpa_base = 0;

	return 0;
}

static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
{
	struct xe_device *xe = gt_to_xe(gt);
	u64 offset;
	u32 reg;

	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
	if (!fw_ref.domains)
		return -ETIMEDOUT;

	if (GRAPHICS_VER(xe) >= 20) {
		u64 ccs_size = tile_size / 512;
		u64 offset_hi, offset_lo;
		u32 nodes, num_enabled;

		reg = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
		nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
		num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */

		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);
		offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);

		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);
		offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);

		offset = offset_hi << 32; /* HW view bits 39:32 */
		offset |= offset_lo << 6; /* HW view bits 31:6 */
		offset *= num_enabled; /* convert to SW view */

		drm_info(&xe->drm, "FLAT_CCS base:%llx, aligned:%s\n", offset,
			 str_yes_no(IS_ALIGNED(offset, SZ_128K)));

		/*
		 * Everything below this offset is handed to the VRAM
		 * allocator, so it has to be the *first* address the
		 * compression hardware owns, rounded down.  Rounding it up
		 * publishes CCS storage as free memory.
		 */
		offset = round_down(offset, SZ_4K);

		/*
		 * CCS storage must not run into GSM.  The old check compared
		 * the offset against GSMBASE - ccs_size for equality, which
		 * could not fail: that value is 128K aligned, so it agreed
		 * with the rounded-up offset even when the base was not 128K
		 * aligned - exactly the case this fixes.
		 */
		xe_assert_msg(xe, offset + ccs_size <=
			      xe_mmio_read64_2x32(&gt_to_tile(gt)->mmio, GSMBASE),
			      "CCS overlaps GSM.\n");
	} else {
		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
		offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
	}

	*poffset = offset;

	return 0;
}

/*
 * tile_vram_size() - Collect vram size and offset information
 * @tile: tile to get info for
 * @vram_size: available vram (size - device reserved portions)
 * @tile_size: actual vram size
 * @tile_offset: physical start point in the vram address space
 *
 * There are 4 places for size information:
 * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1)
 * - TILEx size (actual vram size)
 * - GSMBASE offset (TILEx - "stolen")
 * - CSSBASE offset (TILEx - CSS space necessary)
 *
 * CSSBASE is always a lower/smaller offset then GSMBASE.
 *
 * The actual available size of memory is to the CCS or GSM base.
 * NOTE: multi-tile bases will include the tile offset.
 *
 */
static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
			  u64 *tile_size, u64 *tile_offset)
{
	struct xe_device *xe = tile_to_xe(tile);
	struct xe_gt *gt = tile->primary_gt;
	u64 offset;
	u32 reg;

	if (IS_SRIOV_VF(xe)) {
		struct xe_tile *t;
		int id;

		offset = 0;
		for_each_tile(t, xe, id)
			for_each_if(t->id < tile->id)
				offset += xe_tile_sriov_vf_lmem(t);

		*tile_size = xe_tile_sriov_vf_lmem(tile);
		*vram_size = *tile_size;
		*tile_offset = offset;

		return 0;
	}

	/* actual size */
	if (unlikely(xe->info.platform == XE_DG1)) {
		*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
		*tile_offset = 0;
	} else {
		reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));
		*tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G;
		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
	}

	/* minus device usage */
	if (xe->info.has_flat_ccs) {
		int ret = get_flat_ccs_offset(gt, *tile_size, &offset);

		if (ret)
			return ret;
	} else {
		offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
	}

	/* remove the tile offset so we have just the available size */
	*vram_size = offset - *tile_offset;

	return 0;
}

static void vram_fini(void *arg)
{
	struct xe_device *xe = arg;
	struct xe_tile *tile;
	int id;

	xe_assert(xe, !xe->mem.vram->mapping);

	for_each_tile(tile, xe, id) {
		tile->mem.vram->mapping = NULL;
		if (tile->mem.kernel_vram)
			tile->mem.kernel_vram->mapping = NULL;
	}
}

struct xe_vram_region *xe_vram_region_alloc(struct xe_device *xe, u8 id, u32 placement)
{
	struct xe_vram_region *vram;
	struct drm_device *drm = &xe->drm;

	xe_assert(xe, id < xe->info.tile_count);

	vram = drmm_kzalloc(drm, sizeof(*vram), GFP_KERNEL);
	if (!vram)
		return NULL;

	vram->xe = xe;
	vram->id = id;
	vram->placement = placement;
#if defined(CONFIG_DRM_XE_PAGEMAP)
	vram->migrate = xe->tiles[id].migrate;
#endif
	return vram;
}

static void print_vram_region_info(struct xe_device *xe, struct xe_vram_region *vram)
{
	struct drm_device *drm = &xe->drm;

	if (vram->io_size < vram->usable_size)
		drm_info(drm, "Small BAR device\n");

	drm_info(drm,
		 "VRAM[%u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n",
		 vram->id, &vram->actual_physical_size, &vram->usable_size, &vram->io_size);
	drm_info(drm, "VRAM[%u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n",
		 vram->id, &vram->dpa_base, vram->dpa_base + (u64)vram->actual_physical_size,
		 &vram->io_start, vram->io_start + (u64)vram->io_size);
}

static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram,
			    struct xe_vram_region *lmem_bar, u64 offset, u64 usable_size,
			    u64 region_size, resource_size_t remain_io_size)
{
	/* Check if VRAM region is already initialized */
	if (vram->mapping)
		return 0;

	vram->actual_physical_size = region_size;
	vram->io_start = lmem_bar->io_start + offset;
	vram->io_size = min_t(u64, usable_size, remain_io_size);

	if (!vram->io_size) {
		drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
		return -ENODEV;
	}

	if (vram != xe->mem.vram) {
		struct pci_dev *pdev = to_pci_dev(xe->drm.dev);

		vram->mapping = devm_ioremap_wc(&pdev->dev, vram->io_start, vram->io_size);
		if (!vram->mapping)
			return -ENOMEM;
	}

	vram->dpa_base = lmem_bar->dpa_base + offset;
	vram->usable_size = usable_size;

	print_vram_region_info(xe, vram);

	return 0;
}

/**
 * xe_map_resource_to_region - Map ttm resource to vram memory region
 * @res: The ttm resource
 *
 * Get vram memory region using vram memory manager managing this resource
 *
 * Returns: pointer to xe_vram_region
 */
struct xe_vram_region *xe_map_resource_to_region(struct ttm_resource *res)
{
	struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
	struct ttm_resource_manager *mgr;
	struct xe_ttm_vram_mgr *vram_mgr;

	xe_assert(xe, mem_type_is_vram(res->mem_type));
	mgr = ttm_manager_type(&xe->ttm, res->mem_type);
	vram_mgr = to_xe_ttm_vram_mgr(mgr);

	return container_of(vram_mgr, struct xe_vram_region, ttm);
}

/**
 * xe_vram_probe() - Probe VRAM configuration
 * @xe: the &xe_device
 *
 * Collect VRAM size and offset information for all tiles.
 *
 * Return: 0 on success, error code on failure
 */
int xe_vram_probe(struct xe_device *xe)
{
	struct xe_tile *tile;
	struct xe_vram_region lmem_bar;
	resource_size_t remain_io_size;
	u64 available_size = 0;
	u64 total_size = 0;
	int err;
	u8 id;

	if (!IS_DGFX(xe))
		return 0;

	err = determine_lmem_bar_size(xe, &lmem_bar);
	if (err)
		return err;
	drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &lmem_bar.io_start, &lmem_bar.io_size);

	remain_io_size = lmem_bar.io_size;

	for_each_tile(tile, xe, id) {
		u64 region_size;
		u64 usable_size;
		u64 tile_offset;

		err = tile_vram_size(tile, &usable_size, &region_size, &tile_offset);
		if (err)
			return err;

		total_size += region_size;
		available_size += usable_size;

		err = vram_region_init(xe, tile->mem.vram, &lmem_bar, tile_offset, usable_size,
				       region_size, remain_io_size);
		if (err)
			return err;

		if (total_size > lmem_bar.io_size) {
			drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
				 &total_size, &lmem_bar.io_size);
		}

		remain_io_size -= min_t(u64, tile->mem.vram->actual_physical_size, remain_io_size);
	}

	err = vram_region_init(xe, xe->mem.vram, &lmem_bar, 0, available_size, total_size,
			       lmem_bar.io_size);
	if (err)
		return err;

	return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe);
}

/**
 * xe_vram_region_io_start - Get the IO start of a VRAM region
 * @vram: the VRAM region
 *
 * Return: the IO start of the VRAM region, or 0 if not valid
 */
resource_size_t xe_vram_region_io_start(const struct xe_vram_region *vram)
{
	return vram ? vram->io_start : 0;
}

/**
 * xe_vram_region_io_size - Get the IO size of a VRAM region
 * @vram: the VRAM region
 *
 * Return: the IO size of the VRAM region, or 0 if not valid
 */
resource_size_t xe_vram_region_io_size(const struct xe_vram_region *vram)
{
	return vram ? vram->io_size : 0;
}

/**
 * xe_vram_region_dpa_base - Get the DPA base of a VRAM region
 * @vram: the VRAM region
 *
 * Return: the DPA base of the VRAM region, or 0 if not valid
 */
resource_size_t xe_vram_region_dpa_base(const struct xe_vram_region *vram)
{
	return vram ? vram->dpa_base : 0;
}

/**
 * xe_vram_region_usable_size - Get the usable size of a VRAM region
 * @vram: the VRAM region
 *
 * Return: the usable size of the VRAM region, or 0 if not valid
 */
resource_size_t xe_vram_region_usable_size(const struct xe_vram_region *vram)
{
	return vram ? vram->usable_size : 0;
}

/**
 * xe_vram_region_actual_physical_size - Get the actual physical size of a VRAM region
 * @vram: the VRAM region
 *
 * Return: the actual physical size of the VRAM region, or 0 if not valid
 */
resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region *vram)
{
	return vram ? vram->actual_physical_size : 0;
}
EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);

#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
static void memtest_bo_cleanup(void *arg)
{
	struct xe_device *xe = arg;

	xe_vram_free_memtest_bos(xe);
}

int xe_vram_reserve_memtest_bo(struct xe_device *xe)
{
	struct xe_tile *tile;
	u8 id;

	if (IS_SRIOV_VF(xe))
		return 0;

	for_each_tile(tile, xe, id) {
		u64 vram_size;

		if (!tile->mem.vram)
			continue;

		if (tile->mem.vram->io_size < tile->mem.vram->usable_size) {
			drm_info(&xe->drm,
				 "Tile %d: Small-BAR system detected, skipping VRAM memtest\n",
				 id);
			continue;
		}

		vram_size = tile->mem.vram->usable_size;

		tile->mem.memtest_bo = xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
								    vram_size - SZ_64K,
								    ttm_bo_type_kernel,
								    XE_BO_FLAG_VRAM_IF_DGFX(tile),
								    0, false);
		if (IS_ERR(tile->mem.memtest_bo)) {
			drm_warn(&xe->drm, "Tile %d: Failed to reserve memtest BO\n", id);
			tile->mem.memtest_bo = NULL;
			continue;
		}

		drm_info(&xe->drm, "Tile %d: Reserved memtest BO at offset 0x%llx\n",
			 id, vram_size - SZ_64K);
	}

	return devm_add_action_or_reset(xe->drm.dev, memtest_bo_cleanup, xe);
}

void xe_vram_free_memtest_bos(struct xe_device *xe)
{
	struct xe_tile *tile;
	u8 id;

	for_each_tile(tile, xe, id) {
		if (tile->mem.memtest_bo) {
			xe_bo_unpin_map_no_vm(tile->mem.memtest_bo);
			tile->mem.memtest_bo = NULL;
		}
	}
}

int xe_vram_memtest(struct xe_device *xe)
{
	struct xe_tile *tile;
	u8 id;
	int err = 0;

	if (IS_SRIOV_VF(xe))
		return 0;

	for_each_tile(tile, xe, id) {
		struct xe_bo *last_page_bo = tile->mem.memtest_bo;
		struct dma_fence *fence;
		bool overlap = false;
		int i;
		u8 val;

		if (!last_page_bo || !tile->migrate)
			continue;

		drm_info(&xe->drm, "Tile %d: Running VRAM memtest...\n", id);

		/* CPU write and readback first and last byte of the last page */
		xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
		xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1, u8, 0x5A);

		val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
		if (drm_WARN(&xe->drm, val != 0xA5,
			     "Tile %d: CPU memtest failed at offset 0 (expected 0xA5, got 0x%02x)\n",
			     id, val)) {
			err = -EIO;
			goto unpin;
		}

		val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K - 1, u8);
		if (drm_WARN(&xe->drm, val != 0x5A,
			     "Tile %d: CPU memtest failed at offset 65535 (expected 0x5A, got 0x%02x)\n",
			     id, val)) {
			err = -EIO;
			goto unpin;
		}

		/* Non-CCS access via GPU on the last page */
		xe_bo_lock(last_page_bo, false);
		fence = xe_migrate_clear(tile->migrate, last_page_bo,
					 last_page_bo->ttm.resource,
					 XE_MIGRATE_CLEAR_FLAG_BO_DATA);
		xe_bo_unlock(last_page_bo);

		if (!IS_ERR(fence)) {
			dma_fence_wait(fence, false);
			dma_fence_put(fence);
		} else {
			err = PTR_ERR(fence);
			goto unpin;
		}

		val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
		if (drm_WARN(&xe->drm, val != 0x00,
			     "Tile %d: GPU memtest clear failed at offset 0 (expected 0x00, got 0x%02x)\n",
			     id, val)) {
			err = -EIO;
			goto unpin;
		}

		/*
		 * Check for CCS overlap on the root tile.
		 *
		 * TODO: maybe extend if we ever get multi-tile + CCS. Pay
		 * special attention to the l2 flush below. Currently that is
		 * hard coded to the root tile.
		 */
		if (!id && xe_device_has_flat_ccs(xe) &&
		    GRAPHICS_VERx100(xe) >= 2000) {
			struct xe_bo *scratch_bo_before;
			struct xe_bo *scratch_bo_after;

			scratch_bo_before = xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
								      ttm_bo_type_kernel,
								      XE_BO_FLAG_VRAM_IF_DGFX(tile),
								      false);
			if (IS_ERR(scratch_bo_before)) {
				err = PTR_ERR(scratch_bo_before);
				goto unpin;
			}

			scratch_bo_after = xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
								     ttm_bo_type_kernel,
								     XE_BO_FLAG_VRAM_IF_DGFX(tile),
								     false);
			if (IS_ERR(scratch_bo_after)) {
				xe_bo_unpin_map_no_vm(scratch_bo_before);
				err = PTR_ERR(scratch_bo_after);
				goto unpin;
			}

			/* Save original CCS metadata for PA 0 + */
			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_before, false);
			if (err) {
				xe_bo_unpin_map_no_vm(scratch_bo_before);
				xe_bo_unpin_map_no_vm(scratch_bo_after);
				goto unpin;
			}

			/*
			 * Fill last page. If there is CCS overlap in the last
			 * page this will snag the raw CCS storage.
			 */
			xe_map_memset(xe, &last_page_bo->vmap, 0, 0x5A, SZ_64K);
			xe_device_wmb(xe);

			/*
			 * Global invalidation. Some BMG SKUs will cache the BAR
			 * writes in the GPU side VRAM cache. Make sure above
			 * writes are fully flushed out to VRAM, so this is
			 * hopefully more well behaved with the CCS unit, if
			 * there is indeed CCS overlap with normal VRAM. Since
			 * there is a separate CCS cache, the CCS unit might not
			 * respect the GPU VRAM cache for CCS accesses, so opt
			 * for being super careful here.
			 */
			xe_device_l2_flush(xe, true);

			/* Use GPU to clear CCS state for PA 0 */
			xe_map_memset(xe, &scratch_bo_after->vmap, 0, 0x00, SZ_64K);
			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_after, true);
			if (err) {
				xe_bo_unpin_map_no_vm(scratch_bo_before);
				xe_bo_unpin_map_no_vm(scratch_bo_after);
				goto unpin;
			}
			/*
			 * Global invalidation. Ensure CCS caches really are
			 * nuked and the raw CCS data is visible in VRAM, for
			 * the below access.
			 */
			xe_device_l2_flush(xe, true);

			/* Check if last_page_bo was corrupted by the GPU CCS clear */
			for (i = 0; i < SZ_64K; i += 8) {
				u64 payload = xe_map_rd(xe, &last_page_bo->vmap, i, u64);

				if (payload != 0x5A5A5A5A5A5A5A5AULL) {
					overlap = true;
					break;
				}
			}

			/* Restore original CCS metadata for PA 0 + */
			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_before, true);
			if (err)
				drm_warn(&xe->drm, "Failed to restore CCS metadata\n");

			xe_bo_unpin_map_no_vm(scratch_bo_before);
			xe_bo_unpin_map_no_vm(scratch_bo_after);
		}

		if (drm_WARN(&xe->drm, overlap,
			     "Tile %d: VRAM bounds overlap CCS region! VRAM sizing is incorrect.\n",
			     id)) {
			err = -EINVAL;
			goto unpin;
		}

		drm_info(&xe->drm, "Tile %d: VRAM memtest completed.\n", id);

unpin:
		if (err)
			break;
	}

	xe_vram_free_memtest_bos(xe);

	return err;
}
#endif