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| author | Jan Havran (Advantech Czech) <havran.jan@email.cz> | 2026-09-07 15:48:18 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-09-09 17:59:33 -0700 |
| commit | 59fb389ad6bf50916189e56dafcd225ab977f874 (patch) | |
| tree | 0265d8482452d3dd124e7c4364bc9c9496ff891f /scripts/basic | |
| parent | b824476c56a153934c67c9e0f873e1fd967743d6 (diff) | |
| download | linux-59fb389ad6bf50916189e56dafcd225ab977f874.tar.gz linux-59fb389ad6bf50916189e56dafcd225ab977f874.zip | |
net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value
Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
the reserved value.
Set FCONTX_EN to 0x0080. The register is shared by all supported parts.
Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Link: https://patch.msgid.link/20260907134818.16670-4-havran.jan@email.cz
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'scripts/basic')
0 files changed, 0 insertions, 0 deletions