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path: root/drivers/pinctrl/qcom
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2026-08-24Merge tag 'pinctrl-v7.3-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...
2026-08-16Merge tag 'pinctrl-qcom-updates-for-v7.3-rc1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel Qualcomm pinctrl updates for v7.3-rc1 New drivers: - add pinctrl drivers for Maili TLMM and Elize LPASS LPI TLMM controllers Driver updates: - acknowledge interrupts for the PDC interrupt controller in pinctrl-msm - implement irq_get/set_irqchip_state() for pinctrl-msm - add support for a new model to Qualcomm pinctrl-spmi-gpio - drop some dead code from qcom pinctrl modules Devicetree bindings: - document new TLMM controllers and the new model for the SPMI GPIO Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-16Merge tag 'pinctrl-qcom-fixes-for-v7.2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel Qualcomm pin control fixes for v7.2 - fix intr_target_width for summary interrupt routing in pinctrl-shikra Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-06pinctrl: Use IRQ trigger mask helpersMaulik Shah
Use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH instead of open-coded trigger type combinations in irqchip callbacks. No functional change intended. Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-03Merge tag 'pinctrl-qcom-fixes-for-v7.2-rc6' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into fixes Qualcomm pin control fixes for v7.2-rc6 - mark gpio and pci reset as a GPIO pin functions in pinctrl-ipq8064 - fix audio_sec_mclk_in1/out1 pin numbers in pinctrl-ipq9650 Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-07-31pinctrl: qcom: shikra: Fix intr_target_width for summary interrupt routingKomal Bajaj
The intr_target_width field sets the mask width used when writing target processor into interrupt config register and deciding which processor receives summary interrupt for a given GPIO. Without it, pinctrl driver defaults to a 3-bit mask. On Shikra, this field is 4 bits wide, which could corrupt adjacent bits and mis-route interrupts. Set intr_target_width = 4 to match the hardware. Fixes: 9db68ec534c5 ("pinctrl: qcom: Add Shikra pinctrl driver") Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260728-shikra-pinctrl-intr-width-v1-1-46583734d808@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-28pinctrl: qcom: ipq806x: mark pci reset as a GPIO pin functionHans Ulli Kroll
The qcom pinctrl core supports marking functions that represent GPIO mode via PINCTRL_GPIO_PINFUNCTION(), so that strict pinmuxing does not reject GPIO requests for pins that are muxed to the GPIO function. Mark PCIe reset as GPIO pin function This allows ipq806x to keep the PCIe-reset related configuration in DTS without tripping over strict pinmux ownership checks. Fixes: cc85cb96e2e4 ("pinctrl: qcom: make the pinmuxing strict") Signed-off-by: Hans Ulli Kroll <linux@ulli-kroll.de> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260719134548.8830-3-linux@ulli-kroll.de Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-28pinctrl: qcom: ipq806x: mark gpio as a GPIO pin functionHans Ulli Kroll
The qcom pinctrl core supports marking functions that represent GPIO mode via PINCTRL_GPIO_PINFUNCTION(), so that strict pinmuxing does not reject GPIO requests for pins that are muxed to the GPIO function. Add a IPQ_GPIO_PIN_FUNCTION() helper and use it for the ipq806x gpio function, matching how the msm-based qcom drivers handle this. This allows ipq806x to keep the GPIO-related configuration in DTS without tripping over strict pinmux ownership checks. Fixes: cc85cb96e2e4 ("pinctrl: qcom: make the pinmuxing strict") Signed-off-by: Hans Ulli Kroll <linux@ulli-kroll.de> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260719134548.8830-2-linux@ulli-kroll.de Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-27Merge tag 'pinctrl-v7.2-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "The most interesting commit is the S4 fix for AMD, which probably is helpful to a whole bunch of important machines. - Wakeup nits on the Qualcomm SC8280XP - Double-free issues on the device tree parsing error path - Fixup of the S4 sleep state handling on AMD pin control - Missing Kconfig select REGMAP_MMIO for the Microchip driver leading to compile stalls - Missing Kconfig select GENERIC_PINCONF for the Bitmain BM1880 leading to compile stalls" * tag 'pinctrl-v7.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: bm1880: add missing select GENERIC_PINCONF pinctrl-amd: Don't clear S4 wake bits at probe pinctrl: microchip-sgpio: add missing select REGMAP_MMIO pinctrl: devicetree: don't free uninitialized dev_name on error path pinctrl: qcom: sc8280xp: Add missing wakeup entries for GPIO143/151 pinctrl: qcom: Unconditionally mark gpio as wakeup enable
2026-07-27pinctrl: qcom: ipq9650: fix audio_sec_mclk_in1/out1 group pinsTaceddin Sancak
The audio_sec_mclk_in1 and audio_sec_mclk_out1 groups both list "gpio37", but in the pingroup table those functions are muxed on gpio39, while gpio37 provides the audio_sec_mclk_in0/out0 variants. This makes both functions unusable: selecting them on gpio39 is rejected by the pinmux core because the group is not listed for the function, and selecting them on gpio37 trips the WARN_ON() in msm_pinmux_set_mux() and fails with -EINVAL because that group cannot mux them. Point both groups at gpio39, matching the pingroup table. This also mirrors the primary audio MCLK pair, where the mclk0 and mclk1 variants live on separate pins (gpio53 and gpio51 respectively). Fixes: 3c8e7ba0e399 ("pinctrl: qcom: Introduce IPQ9650 TLMM driver") Assisted-by: Claude:claude-fable-5 Signed-off-by: Taceddin Sancak <ts.solidarity@gmail.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260718002146.698973-1-ts.solidarity@gmail.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-27pinctrl: qcom: Add irq_get/set_irqchip_state() for msm gpio irqchipMaulik Shah
MPM irqchip monitors the interrupts during SoC sleep state and after wakeup replays the edge interrupt by making it pending at respective irqchip by invoking irq_set_irqchip_state() API. The msm gpio irqchip however do not implement this function making it impossible to replay the gpio interrupt on any MPM irqchip based SoC. Add the missing irq_get/set_irqchip_state() APIs. Implement only IRQCHIP_STATE_PENDING case which MPM irqchip uses. Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Navya Malempati <navya.malempati@oss.qualcomm.com> Link: https://patch.msgid.link/20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-16pinctrl: qcom: milos-lpass-lpi: Add Eliza LPASS LPI TLMMRavi Hothi
Eliza SoC has the same LPASS LPI pin mux functions as Milos but the slew rate control is in the same GPIO config register rather than a separate register. Add a new variant data struct with updated slew offsets and LPI_FLAG_SLEW_RATE_SAME_REG flag, reusing the existing pin descriptors and function table from Milos. Signed-off-by: Ravi Hothi <ravi.hothi@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260715132150.1322663-3-ravi.hothi@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-08Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"Maulik Shah
This reverts commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"). PDC interrupts no more break GPIOs PDC irqchip is updated to work for pass through or secondary mode. Update nwakeirq_map to reflect the GPIO to PDC irq map size. Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-6-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-08pinctrl: qcom: Acknowledge IRQs for PDC interrupt controllerStephan Gerhold
PDC needs to acknowledge incoming GPIO interrupts to clear the latched interrupt status in secondary mode of PDC. For level-triggered IRQs this happens automatically in irq_eoi() but for edge-triggered IRQs this needs to happen as early as possible in the IRQ handler. Implement this by using handle_fasteoi_ack_irq() as IRQ handler in this situation and forward the irq_ack() callback to the parent IRQ chip. Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-5-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-03Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c ↵Uwe Kleine-König (The Capable Hub)
files) Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
2026-07-01pinctrl: qcom: Add the tlmm driver for Maili platformJingyi Wang
Add support for Maili TLMM configuration and control via the pinctrl framework. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260622-maili-pinctrl-v3-2-9724e1000471@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-07-01pinctrl: qcom: sc8280xp: Add missing wakeup entries for GPIO143/151Konrad Dybcio
Pins 143 and 151 were not included in the PDC wakeup map. They are normally used for PCIe2A and PCIe3a PERST# respectively, so they're unlikely to be excercised in practice, but still add them for the sake of completeness. Fixes: c0e4c71a9e7c ("pinctrl: qcom: Introduce sc8280xp TLMM driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260626-topic-8280_pinctrl_wakeup-v1-1-2ccb267148f5@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-30pinctrl: qcom: Unconditionally mark gpio as wakeup enableSneh Mankad
GPIO interrupts that are wakeup capable need to be forwarded to wakeup capable parent irqchip. This is done via writing to it's wakeup_enable bit. Currently the bit is set only for PDC irqchip by checking skip_wake_irqs. skip_wake_irqs is set to differentiate between parent irqchips MPM and PDC. It is set when the parent irqchip is PDC to inform pinctrl about skipping the IRQ setting up at TLMM. However, the functionality to forward GPIO interrupts during SoC low power mode is needed regardless of which parent irqchip it is. Without the functionality it is impossible for MPM irqchip to detect the GPIO interrupt during SoC low power mode since for MPM irqchip the skip_wake_irqs is always false. Remove skip_wake_irqs condition when setting wakeup enable bit to allow forwarding GPIO interrupts for SoCs using MPM irqchip too. Fixes: 76b446f5b86e ("pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits") Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260616-enable_wakeup_capable_gpios-v3-1-fb59647d89cb@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-30pinctrl: qcom: Drop unused irq_data argument from ↵Hans de Goede
msm_gpio_update_dual_edge_pos() The "struct irq_data *d" argument to msm_gpio_update_dual_edge_pos() is unused, drop it. Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260623122732.6439-2-johannes.goede@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-30pinctrl: qcom: Drop unnecessary bitmap_fill() callHans de Goede
Drop an unnecessary bitmap_fill() call from msm_gpio_irq_init_valid_mask(), this is unnecessary because gpiochip_allocate_mask() already does this. Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260623122732.6439-1-johannes.goede@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-30pinctrl: qcom: spmi-gpio: Add PMG1110 GPIO supportFenglin Wu
Add PMG1110 GPIO support with its compatible string and match data. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260610-pmg1110-gpio-v1-2-a9c50cd8b5d9@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-26pinctrl: qcom: Avoid assigning unused private context in test casesSneh Mankad
tlmm_test_rising_while_disabled() sets thread_op_remain to 10, but this variable is only used by the threaded IRQ handler to control the number of GPIO pin toggles. Since tlmm_test_rising_while_disabled() does not register a threaded IRQ handler, the assignment is never used. Similarly, tlmm_test_high() and tlmm_test_low() set intr_op_remain to 9, but the variable is used to denote the IRQ handler the number of times GPIO signal has to be toggled from the hard IRQ handler. Since tlmm_test_high() and tlmm_test_low() themselves toggle the signal and do not require the hard IRQ handler to do it, the assignment is never used. Remove the thread_op_remain assignment from tlmm_test_rising_while_disabled() and intr_op_remain assignment from tlmm_test_high() and tlmm_test_low() test cases. This does not cause any change in functionality. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Link: https://patch.msgid.link/20260610-tlmm_test_changes-v2-1-f34536da4717@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-18Merge tag 'pinctrl-v7.2-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - Add new generic callbacks to populate per-pin pin controllers creating groups and functions from the device tree building out pinctrl_generic_to_map() and move the Spacemit driver over to use this - Generic board-level pin control driver using the mux framework New pin controller drivers: - Amlogic (meson) A9 SoC - Aspeed AST2700 SoC0 and SoC1 - nVidia Tegra264 and Tegra238 - Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM - Renesas RZ/G3L SoC - UltraRISC DP1000 Improvements: - Handle pull up/pull down properly in the Renesas RZG2L driver - Fix up nVidia Tegra 234 DT bindings - Fix up pin definitions in the Qualcomm Eliza driver - Qualcomm PM8010 GPIO support in the PM8010 - Qualcomm SM6115 EGPIO support in the SM6115 - Switch Qualcomm LPASS LPI drivers to use runtime PM for power management - Clean up the Qualcomm Kconfig business a bit to include the necessary drivers for each subarch - Fix output glitch in the Amlogic (meson) A4 pin controller - Move the Airoha driver from the Mediatek directory to its own directory. It is too different from other Mediatek hardware - A slew of fixes to the Airoha AN7581 and AN7583 drivers" * tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits) pinctrl: Export pinctrl_get_group_selector() pinctrl: Match DT helper types pinctrl: qcom: Register functions before enabling pinctrl pinctrl: meson: amlogic-a4: use nolock get range pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller pinctrl: qcom: Remove unused macro definitions pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA pinctrl: tegra238: add missing AON pin groups dt-bindings: pinctrl: tegra238: add missing AON pin groups pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function pinctrl: airoha: an7583: fix phy1_led1 pin function pinctrl: airoha: an7583: add missed gpio22 pin group pinctrl: airoha: an7583: fix gpio21 pin group pinctrl: airoha: fix pwm pin function for an7581 and an7583 pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7583: fix misprint in gpio19 pinconf pinctrl: airoha: an7581: fix misprint in gpio19 pinconf ...
2026-06-11pinctrl: qcom: Register functions before enabling pinctrlAlexandre MINETTE
pinctrl consumers can request states while the pinctrl core enables the controller. On Qualcomm pinctrl drivers this can happen before the SoC function list has been registered, which leaves the function table incomplete during state lookup. On APQ8064 this can fail while claiming pinctrl hogs: apq8064-pinctrl 800000.pinctrl: invalid function ps_hold in map table apq8064-pinctrl 800000.pinctrl: error claiming hogs: -22 apq8064-pinctrl 800000.pinctrl: could not claim hogs: -22 Register Qualcomm pinctrl with devm_pinctrl_register_and_init(), add the SoC pin functions, and only then enable the pinctrl device. Signed-off-by: Alexandre MINETTE <contact@alex-min.fr> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: qcom: Remove unused macro definitionsNavya Malempati
The macros QUP_I3C and UFS_RESET are defined in some platforms and yet not used. Remove these macros as they are unnecessary. Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-10pinctrl: qcom: eliza: Add missing sdc2 pin function mappingsAbel Vesa
GPIOs 38, 39, 48 and 49 support the SDC2 DATA function, while GPIO 51 supports SDC2 CMD and GPIO 62 supports SDC2 CLK. However, the sdc2 pin function is not listed in the corresponding pingroup definitions, preventing these pins from being muxed for SDC2 operation. Add the missing sdc2 function mappings. Fixes: 6f26989e15fb ("pinctrl: qcom: Add Eliza pinctrl driver") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-10pinctrl: qcom: lpass-lpi: drop unused runtime-PM write helperAjay Kumar Nandam
lpi_gpio_write() became unused after the PM clock runtime conversion switched write paths to register helper calls inside callers that already hold an active runtime-PM reference. With -Werror this triggers: error: 'lpi_gpio_write' defined but not used [-Wunused-function] Drop the dead wrapper and rename the low-level MMIO helpers from __lpi_gpio_* to lpi_gpio_*_reg for neutral register-accessor naming. Fixes: b719ede389d8 ("pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM") Reported-by: Nathan Chancellor <nathan@kernel.org> Closes: https://lore.kernel.org/all/f03850f6-186d-4988-a450-e6e95f24a551@kernel.org/ Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-08pinctrl: qcom: Fix resolving register base address from device nodeSneh Mankad
Commit 56ffb63749f4 ("pinctrl: qcom: add multi TLMM region option parameter") added reg-names property based register reading. However multiple platforms are not using the reg-names as they have only single TLMM register region. Commit tried to handle this using the default_region module parameter, however this condition is unreachable as the error return precedes it by just checking if reg-names property exists or not, making it impossible to use tlmm-test for the SoCs (x1e80100) which don't have reg-names property in TLMM device. Fix this by moving the default_region check at the start of the tlmm_reg_base(). Fixes: 56ffb63749f4 ("pinctrl: qcom: add multi TLMM region option parameter") Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-08pinctrl: qcom: Modify MSM_PULL_MASK to accurately represent PULL bitsSneh Mankad
MSM_PULL_MASK currently spans bits [2:0], but the GPIO_PULL field in the GPIO_CFG register only occupies bits [1:0]. Bit 2 belongs to FUNC_SEL. MSM_PULL_MASK is used to isolate the GPIO_PULL bits before writing the pull configuration (PULL_DOWN: 0x1, PULL_UP: 0x3) to the GPIO_CFG register. Narrow it to bits [1:0] to prevent unintended modification of the FUNC_SEL field. This causes no functional change since the driver currently does not modify the FUNC_SEL bit, but align the mask with hardware configuration nonetheless. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-08pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PMAjay Kumar Nandam
Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Guard GPIO register read/write helpers and slew-rate register programming with synchronous runtime PM calls so the device is active during MMIO operations whenever autosuspend is enabled. Make PINCTRL_LPASS_LPI depend on PM_CLK, since this patch introduces direct PM clock API use in the shared core. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-08pinctrl: qcom: lpass-lpi: Enable runtime PM hooks on LPASS LPI SoCsAjay Kumar Nandam
The LPASS LPI core conversion to PM clock framework relies on variant drivers wiring runtime PM callbacks. Hook up runtime PM callbacks for the LPASS LPI variant drivers touched in this patch so they are prepared for the shared core conversion. This commit is a preparatory NOP on its own, as runtime PM is still disabled on these devices until the following core conversion patch. This is a mechanical per-variant driver update that relies on the same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/ pm_clk_resume()) and DT-provided clocks. Runtime behavior was validated on Kodiak (sc7280). Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-29pinctrl: qcom: Replace open coded eoi call with irq_chip_eoi_parent()Maulik Shah
Before commit 14dbe186b9d4 ("pinctrl: msmgpio: Make the irqchip immutable") msm gpio irqchip conditionally initialized pctrl->irq_chip.irq_eoi to irq_chip_eoi_parent() only for the GPIO irqs having a wakeup capable irq. In order to make gpio irqchip immutable pctrl->irq_chip.irq_eoi is initialized to msm_gpio_irq_eoi() which now gets invoked for both wake up and non-wakeup capable GPIO IRQs. Replace open coded eoi call to parent irqchip with irq_chip_eoi_parent(). Since the irq_chip_*_parent() APIs internally do not check the valid parent data is present to ensure irq_chip_eoi_parent() is only invoked for wakeup capable GPIOs validate d->parent_data within msm_gpio_irq_eoi(). For non wakeup capable GPIOs d->parent_data will be NULL since parent irqchip diconnects hierarchy using irq_domain_disconnect_hierarchy() and later irq framework trims hierarchy using irq_domain_trim_hierarchy() which makes d->parent_data as NULL. No functional impact. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-27pinctrl: qcom: sm6115: Add egpio supportStanislav Zaikin
This mirrors the egpio support added to sc7280/sm8450/sm8250/etc. This change is necessary for GPIOs 98-112 (15 GPIOs) to be used as normal GPIOs. Signed-off-by: Stanislav Zaikin <zstaseg@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-23pinctrl: qcom: eliza: Merge QUP1_SE4 lanes in groupsAbel Vesa
QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs. The current driver exposes lanes 0, 1, 2 and 3 as independent functions. However, since these are usually configured in pairs in devicetree, it makes more sense to merge them into groups. So merge the per-lane functions into qup1_se4_01 and qup1_se4_23, and list both GPIO36 and GPIO37 in each function group. Fixes: 4f5b1f4e770b ("pinctrl: qcom: eliza: Split QUP1_SE4 lanes") Suggested-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-23pinctrl: qcom: spmi-gpio: Add PM8010 GPIO supportFenglin Wu
Add PM8010 GPIO support with its compatible string and match data. Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-23pinctrl: qcom: Add Shikra pinctrl driverKomal Bajaj
Add pinctrl driver for TLMM block found in Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-11pinctrl: qcom: Fix typoThomas Weber
STRENGH -> STRENGTH Signed-off-by: Thomas Weber <thomas.weber@corscience.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-07pinctrl: qcom: nord: remove duplicated pin functionBartosz Golaszewski
The qdss_cti function is initialized twice in the nord_functions array. Remove the duplicate entry. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202605061633.BJLI5voT-lkp@intel.com/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Make important drivers default (1)Krzysztof Kozlowski
The main SoC TLMM (Top-Level Multiplexer) pin controller drivers are essential for booting up SoCs and are not really optional for a given platform. Kernel should not ask users choice of drivers when that choice is obvious and known to the developers that answer should be 'yes' or 'module'. Switch all Qualcomm TLMM pin controller drivers to a default 'yes' for ARCH_QCOM. This has impact: 1. arm64 defconfig: enable PINCTRL_SM7150, PINCTRL_IPQ9650 and PINCTRL_HAWI, which were not selected before but should be, because these platforms need them for proper boot. 2. arm qcom_defconfig: no changes. 3. arm multi_v7 defconfig: enable drivers necessary to boot ARM 32-bit platforms, which are already enabled on qcom_defconfig. 4. COMPILE_TEST builds: enable by default all drivers for arm or arm64 builds, whenever ARCH_QCOM is selected. This has impact on build time and feels logical, because if one selects ARCH_QCOM then probably by default wants to build test it entirely. Kernels with COMPILE_TEST are not supposed to be used for booting. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> [linusw@kernel.org: Split off the defconfig changes to a separate patch] Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Move MODULE_DEVICE_TABLE next to the table itselfKrzysztof Kozlowski
By convention MODULE_DEVICE_TABLE() immediately follows the ID table it exports, because this is easier to read and verify. It also makes more sense since #ifdef for ACPI or OF could hide both of them. Some Qualcomm pin controller drivers already have this correctly placed, so adjust the other drivers. No functional impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Add SM6350 LPASS LPI TLMMLuca Weiss
Add support for the pin controller block on SM6350 Low Power Island. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> [linusw@kernel.org: fixed up Kconfig entry] Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew controlLuca Weiss
On some platforms like SM6350 (Bitra), some pins have their slew controlled with the SPARE_1 register. Add support for that. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Remove unused macro definitionsMaulik Shah
Remove SDC_QDSD_PINGROUP, QUP_I3C and UFS_RESET macros as on some platforms they are unused. No functional impact. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: qcom: add the TLMM driver for the Nord platformsBartosz Golaszewski
Add support for the TLMM controller on the Qualcomm Nord platform. Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: qcom: Fix wakeirq map by removing disconnected irqs for sm8150Maulik Shah
PDC interrupts 122-125 were meant for ibi_i3c wakeup but sm8150 do not support i3c. GPIOs 39,51,88 and 144 are also connected to different PDC pin and already reflected in the wake irq map. Remove the unsupported wakeup interrupts from the map. Fixes: 90337380c809 ("pinctrl: qcom: sm8150: Specify PDC map") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: Fix GPIO to PDC wake irq map for qcs615Maulik Shah
PDC interrupts 122-125 were meant for ibi_i3c wakeup but qcs615 do not support i3c. GPIOs 39,51,88 and 89 are also connected to different PDC pin to support non-ibi wakeup. Update the wakeirq map to reflect same. Fixes: b698f36a9d40 ("pinctrl: qcom: add the tlmm driver for QCS615 platform") Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: Unify user-visible "Qualcomm" nameKrzysztof Kozlowski
Various names for Qualcomm as a company are used in user-visible config options: QCOM, Qualcomm and Qualcomm Technologies. Switch to unified "Qualcomm" so it will be easier for users to identify the options when for example running menuconfig. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> [linusw@kernel.org: Also fix the new IPQ9650] Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: eliza: Split QUP1_SE4 lanesAlexander Koskovich
QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the function name cannot be the same or the alternate function cannot be selected. Split them up into individual lane functions so boards can specify. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: eliza: Split QUP lane mirror alternatesAlexander Koskovich
Several QUP lanes have MIRA/MIRB mirror routings which are collapsed under a single function name (e.g. qup1_se6). This is an issue because it means there are multiple functions defined for a given pin that share the same name: [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6... So when you select pin 42 and request function qup1_se6, it will select the first instance of it in this group, which just happens to be QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively unreachable. Split each of these lanes that has an alternative GPIO into their own function so they can actually be selected, following the pattern seen in pinctrl-sm8550.c. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: eliza: Fix QDSS trace clock/control pingroup namesAlexander Koskovich
Fix a few typos for these in their respective pingroups, the groups already exist they just weren't referenced. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Fixes: 6f26989e15fb ("pinctrl: qcom: Add Eliza pinctrl driver") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-09 00:23:58 +0000