target/hexagon: decode the DMA insts as unimp

These instructions are used by some guest test cases during system
initialization.  It's handy to unblock some tests for now and we'll
follow up with a full implementation later.

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

5 files changed, 61 insertions, 0 deletions

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 1d25391282..5f7df66ae6 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1329,6 +1329,34 @@
     do { } while (0)
 #define fGEN_TCG_Y2_syncht(SHORTCODE) \
     do { } while (0)
+
+#define fGEN_TCG_DMA_UNIMP() \
+    qemu_log_mask(LOG_UNIMP, "'%s' is not implemented\n", \
+                  opcode_names[insn->opcode])
+#define fGEN_TCG_Y6_dmstart(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); RsV = RsV; } while (0)
+#define fGEN_TCG_Y6_dmresume(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); RsV = RsV; } while (0)
+#define fGEN_TCG_Y6_dmlink(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); RsV = RsV; RtV = RtV; } while (0)
+#define fGEN_TCG_Y6_dmcfgwr(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); RsV = RsV; RtV = RtV; } while (0)
+#define fGEN_TCG_Y6_dmcfgrd(SHORTCODE) \
+    do { \
+        fGEN_TCG_DMA_UNIMP(); \
+        RsV = RsV; \
+        tcg_gen_movi_tl(RdV, 0); \
+    } while (0)
+#define fGEN_TCG_Y6_dmpoll(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); tcg_gen_movi_tl(RdV, 0); } while (0)
+#define fGEN_TCG_Y6_dmwait(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); tcg_gen_movi_tl(RdV, 0); } while (0)
+#define fGEN_TCG_Y6_dmpause(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); tcg_gen_movi_tl(RdV, 0); } while (0)
+#define fGEN_TCG_Y6_dmsyncht(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); tcg_gen_movi_tl(RdV, 0); } while (0)
+#define fGEN_TCG_Y6_dmtlbsynch(SHORTCODE) \
+    do { fGEN_TCG_DMA_UNIMP(); tcg_gen_movi_tl(RdV, 0); } while (0)
 #define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \
     do { \
         RsV = RsV; \
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 1f109d44de..9f53fcb6b9 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -16,6 +16,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "cpu.h"
 #include "internal.h"
 #include "tcg/tcg-op.h"
diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def
index 1c64495d51..d9e8ea2aeb 100644
--- a/target/hexagon/imported/encode_pp.def
+++ b/target/hexagon/imported/encode_pp.def
@@ -529,6 +529,17 @@ DEF_ENC32(Y5_l2fetch,      ICLASS_ST" 011 01 00sssss PP-ttttt --------")
 DEF_ENC32(Y6_l2gcleanpa,   ICLASS_ST" 011 01 01----- PP-ttttt --------")
 DEF_ENC32(Y6_l2gcleaninvpa,ICLASS_ST" 011 01 10----- PP-ttttt --------")
 
+DEF_ENC32(Y6_dmcfgrd,   "10101000000sssssPP------101ddddd")
+DEF_ENC32(Y6_dmcfgwr,   "10101000000sssssPP-ttttt110-----")
+DEF_ENC32(Y6_dmlink,    "10100110000sssssPP-ttttt010-----")
+DEF_ENC32(Y6_dmpause,   "10101000000-----PP------011ddddd")
+DEF_ENC32(Y6_dmpoll,    "10101000000-----PP------010ddddd")
+DEF_ENC32(Y6_dmresume,  "10100110000sssssPP------100-----")
+DEF_ENC32(Y6_dmstart,   "10100110000sssssPP------001-----")
+DEF_ENC32(Y6_dmsyncht,  "10101000000-----PP-----0111ddddd")
+DEF_ENC32(Y6_dmtlbsynch,"10101000000-----PP-----1111ddddd")
+DEF_ENC32(Y6_dmwait,    "10101000000-----PP------001ddddd")
+
 
 /*******************************/
 /*                             */
diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/system.idef
index 9e85bed0a6..02aee8ce8e 100644
--- a/target/hexagon/imported/system.idef
+++ b/target/hexagon/imported/system.idef
@@ -222,6 +222,17 @@ Q6INSN(Y2_isync,"isync",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),"Memory Syn
 Q6INSN(Y2_barrier,"barrier",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK),"Memory Barrier",{fBARRIER();})
 Q6INSN(Y2_syncht,"syncht",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET),"Memory Synchronization",{fSYNCH();})
 
+Q6INSN(Y6_dmstart,"dmstart(Rs32)",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Start",{RsV=RsV;})
+Q6INSN(Y6_dmlink,"dmlink(Rs32,Rt32)",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Link",{RsV=RsV; RtV=RtV;})
+Q6INSN(Y6_dmpoll,"Rd32=dmpoll",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Poll",{RdV=0;})
+Q6INSN(Y6_dmwait,"Rd32=dmwait",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Wait",{RdV=0;})
+Q6INSN(Y6_dmsyncht,"Rd32=dmsyncht",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA SynchT",{RdV=0;})
+Q6INSN(Y6_dmtlbsynch,"Rd32=dmtlbsynch",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA TLB Synch",{RdV=0;})
+Q6INSN(Y6_dmcfgrd,"Rd32=dmcfgrd(Rs32)",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Config Read",{RsV=RsV; RdV=0;})
+Q6INSN(Y6_dmcfgwr,"dmcfgwr(Rs32,Rt32)",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Config Write",{RsV=RsV; RtV=RtV;})
+Q6INSN(Y6_dmpause,"Rd32=dmpause",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Pause",{RdV=0;})
+Q6INSN(Y6_dmresume,"dmresume(Rs32)",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_DMA,A_RESTRICT_SLOT0ONLY,A_NO_TIMING_LOG),"DMA Resume",{RsV=RsV;})
+
 
 Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);})
 Q6INSN(Y2_dckill,"dckill",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_DCFLUSHOP),"Data Cache Invalidate",{fDCKILL();})
diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_info.c.inc
index 11c90f86ad..a91b91a23e 100644
--- a/target/hexagon/tag_rev_info.c.inc
+++ b/target/hexagon/tag_rev_info.c.inc
@@ -575,6 +575,16 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = {
     [J2_jumprh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
     [L2_loadw_aq] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
     [L4_loadd_aq] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmcfgrd] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmcfgwr] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmlink] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmpause] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmpoll] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmresume] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmstart] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmsyncht] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmtlbsynch] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [Y6_dmwait] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
     [M7_dcmpyiw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
     [M7_dcmpyiw_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
     [M7_dcmpyiwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },